{"id":8476,"date":"2019-03-04T15:06:36","date_gmt":"2019-03-04T15:06:36","guid":{"rendered":"https:\/\/hocvienit.vn\/?p=8476"},"modified":"2025-05-15T16:47:49","modified_gmt":"2025-05-15T09:47:49","slug":"phan-tich-mach-cap-nguon-cho-chipset","status":"publish","type":"post","link":"https:\/\/hocvienit.vn\/?p=8476","title":{"rendered":"Ph\u00e2n t\u00edch m\u1ea1ch c\u1ea5p ngu\u1ed3n cho chipset – Ki\u1ebfn th\u1ee9c mainboard"},"content":{"rendered":"

Nh\u01b0 b\u1ea1n \u0111\u00e3 bi\u1ebft tr\u00ean mainboard c\u00f3 3 ngu\u1ed3n \u1ed5n \u00e1p ch\u00ednh \u0111\u00f3 l\u00e0 VRM \u1ed5n \u00e1p ngu\u1ed3n cho CPU, ngu\u1ed3n RAM. So v\u1edbi c\u00e1ch x\u00e1c \u0111\u1ecbnh ngu\u1ed3n c\u1ea5p cho CPU v\u00e0 RAM th\u00ec c\u00e1ch ph\u00e2n t\u00edch m\u1ea1ch c\u1ea5p ngu\u1ed3n cho chipset kh\u00f3 h\u01a1n v\u00ec n\u00f3 ch\u1ee7 y\u1ebfu d\u1ef1a v\u00e0o kinh nghi\u1ec7m.<\/span><\/p>\n

\"Ph\u00e2n
Ph\u00e2n t\u00edch m\u1ea1ch c\u1ea5p ngu\u1ed3n cho chipset – Ki\u1ebfn th\u1ee9c mainboard<\/figcaption><\/figure>\n

B\u1ea1n c\u00f3 th\u1ec3 quan s\u00e1t s\u01a1 \u0111\u1ed3 t\u1ed5ng qu\u00e1t c\u00e1c m\u1ea1ch \u1ed5n \u00e1p ngu\u1ed3n cho chipset d\u01b0\u1edbi \u0111\u00e2y:<\/span><\/p>\n

\"S\u01a1
S\u01a1 \u0111\u1ed3 t\u1ed5ng qu\u00e1t c\u00e1c m\u1ea1ch \u1ed5n \u00e1p ngu\u1ed3n cho chipset<\/figcaption><\/figure>\n

Theo s\u01a1 \u0111\u1ed3 tr\u00ean chip B\u1eafc v\u00e0 chip nam s\u1eed d\u1ee5ng c\u00f9ng l\u00fac r\u1ea5t nhi\u1ec1u ngu\u1ed3n kh\u00e1c nhau. C\u1ee5 th\u1ec3:<\/span><\/p>\n

– Chip B\u1eafc:<\/strong> D\u00f9ng ngu\u1ed3n Vcore, Vcc RAM v\u00e0 d\u00f9ng th\u00eam ngu\u1ed3n 1v5 v\u00e0 1v8<\/span><\/p>\n

– Chip Nam:<\/strong> D\u00f9ng tr\u1ef1c ti\u1ebfp 5V, 3v3 v\u00e0 5V STB t\u1eebng ngu\u1ed3n ch\u00ednh c\u0169ng d\u00f9ng th\u00eam ngu\u1ed3n 1v5 v\u00e0 1v8.<\/span><\/p>\n

C\u00e1ch x\u00e1c \u0111\u1ecbnh m\u1ea1ch ngu\u1ed3n chipset<\/strong><\/h2>\n

Tr\u01b0\u1edbc \u0111\u00f3, b\u1ea1n c\u1ea7n ch\u00fa \u00fd vi\u1ec7c x\u00e1c \u0111\u1ecbnh \u0111\u00fang c\u00e1c m\u1ea1ch \u1ed5n \u00e1p cho chipset tr\u00ean mainboard l\u00e0 t\u01b0\u01a1ng \u0111\u1ed1i ph\u1ee9c t\u1ea1p b\u1edfi:<\/span><\/p>\n

– Ta kh\u00f4ng th\u1ec3 \u0111o v\u00e0o ch\u00e2n c\u1ee7a chipset v\u00ec chipset s\u1eed d\u1ee5ng ch\u00e2n g\u1ea7m.<\/span><\/p>\n

– C\u00e1c m\u1ea1ch in ph\u00eda sau chipset \u0111\u01b0\u1ee3c ph\u1ee7 m\u1ed9t l\u1edbp s\u01a1n c\u00e1ch \u0111i\u1ec7n <\/span><\/p>\n

– Tr\u00ean c\u00e1c \u0111\u1eddi mainboard kh\u00e1c nhau s\u1eed d\u1ee5ng nhi\u1ec1u lo\u1ea1i m\u1ea1ch \u1ed5n \u00e1p kh\u00e1c nhau <\/span><\/p>\n

– C\u00e1c lo\u1ea1i chipset kh\u00e1c nhau s\u1eed d\u1ee5ng nhi\u1ec1u lo\u1ea1i m\u1ea1ch \u1ed5n \u00e1p kh\u00e1c nhau<\/span><\/p>\n

\u0110\u1ec3 c\u00f3 th\u1ec3 x\u00e1c \u0111\u1ecbnh ch\u00ednh x\u00e1c m\u1ea1ch \u1ed5n \u00e1p chipset b\u1ea1n c\u00f3 th\u1ec3 d\u1ef1a v\u00e0o m\u1ed9t s\u1ed1 \u0111\u1eb7c \u0111i\u1ec3m d\u01b0\u1edbi \u0111\u00e2y:<\/span><\/p>\n

– M\u1ea1ch \u1ed5n \u00e1p cho hai chipset th\u01b0\u1eddng n\u1eb1m trong khu v\u1ef1c gi\u1eefa hai chipset<\/span><\/p>\n

– Khi ho\u1ea1t \u0111\u1ed9ng ch\u00e2n S th\u01b0\u1eddng s\u1eed d\u1ee5ng IC 8 ch\u00e2n \u0111\u1ec3 \u0111i\u1ec1u khi\u1ec3n Mosfet.<\/span><\/p>\n

– M\u1ea1ch th\u01b0\u1eddng s\u1eed d\u1ee5ng IC 8 ch\u00e2n \u0111\u1ec3 \u0111i\u1ec1u khi\u1ec3n Mosfet<\/span><\/p>\n

– M\u1ed9t s\u1ed1 Mainboard \u0111\u1eddi m\u1edbi s\u1eed d\u1ee5ng ngu\u1ed3n xung nh\u01b0 m\u1ea1ch VRM c\u1ee7a CPU v\u00ec v\u1eady m\u1ea1ch c\u00f3 c\u00e1c cu\u1ed9n d\u00e2y.<\/span><\/p>\n

\"\u0110\u00e8n
\u0110\u00e8n Mosfet \u1ed5n \u00e1p ngu\u1ed3n cho Chipset<\/figcaption><\/figure>\n
\"\u0110o
\u0110o v\u00e0o ch\u00e2n S c\u1ee7a m\u1ed9t \u0111\u00e8n Mosfet \u0111\u1ee9ng khu v\u1ef1c gi\u1eefa hai Chipset<\/figcaption><\/figure>\n

\u0110o v\u00e0o ch\u00e2n S c\u1ee7a m\u1ed9t \u0111\u00e8n Mosfet \u0111\u1ee9ng khu v\u1ef1c gi\u1eefa hai Chipset <\/span>th\u1ea5y c\u00f3 1,5V ho\u1eb7c 1,8V \u00a0=> \u0111\u00f3 l\u00e0 c\u00e1c \u0111\u00e8n \u1ed5n \u00e1p cho Chipset.<\/span><\/p>\n

M\u1ea1ch \u1ed5n \u00e1p s\u1eed d\u1ee5ng IC dao \u0111\u1ed9ng \u0111i\u1ec1u khi\u1ec3n \u0111\u00e8n Mosfet \u0111\u01a1n<\/strong><\/h2>\n
\"S\u01a1
S\u01a1 \u0111\u1ed3 nguy\u00ean l\u00fd c\u1ee7a m\u1ea1ch \u1ed5n \u00e1p ngu\u1ed3n cho Chipset<\/figcaption><\/figure>\n
\"M\u1ea1ch
M\u1ea1ch \u1ed5n \u00e1p cho c\u00e1c Chipset tr\u00ean v\u1ec9 m\u00e1y<\/figcaption><\/figure>\n

S\u01a1 \u0111\u1ed3 nguy\u00ean l\u00fd c\u1ee7a m\u1ea1ch \u1ed5n \u00e1p ngu\u1ed3n cho Chipset s\u1eed d\u1ee5ng IC dao \u0111\u1ed9ng<\/span><\/p>\n

\"S\u01a1
S\u01a1 \u0111\u1ed3 nguy\u00ean l\u00fd c\u1ee7a m\u1ea1ch \u1ed5n \u00e1p ngu\u1ed3n cho Chipset s\u1eed d\u1ee5ng IC dao \u0111\u1ed9ng<\/figcaption><\/figure>\n

Nguy\u00ean l\u00fd ho\u1ea1t \u0111\u1ed9ng c\u1ee7a m\u1ea1ch:<\/strong> <\/span><\/p>\n

– Khi c\u00f3 ngu\u1ed3n cung c\u1ea5p, IC \u1ed5n \u00e1p s\u1ebd t\u1ea1o \u00a0ra \u0111i\u1ec7n \u00e1p \u0111i\u1ec1u khi\u1ec3n \u1edf ch\u00e2n GATE \u0111\u1ec3 \u0111\u01b0a t\u1edbi \u0111i\u1ec1u khi\u1ec3n ch\u00e2n G c\u1ee7a Mosfet, Mosfet m\u1edf ra \u0111i\u1ec7n \u00e1p 1.5V c\u1ea5p cho c\u00e1c chipset m\u1ea1ch gi\u1eef \u0111\u01b0\u1ee3c \u0111i\u1ec7n \u00e1p ra l\u00e0 gi\u00e1 tr\u1ecb kh\u00f4ng \u0111\u1ed5i nh\u1edd v\u00e0o \u0111\u01b0\u1eddng h\u1ed3i ti\u1ebfp l\u1ea5y t\u1eeb ch\u00e2n S c\u1ee7a \u0111\u00e8n Mosfet, mosfet h\u1ed3i ti\u1ebfp v\u1ec1 ch\u00e2n FB c\u1ee7a IC th\u00f4ng qua c\u1ea7u ph\u00e2n \u00e1p R106 v\u00e0 R107, n\u1ebfu \u0111i\u1ec7n \u00e1p ra t\u0103ng >1,5V th\u00ec \u0111i\u1ec7n \u00e1p h\u1ed3i ti\u1ebfp v\u1ec1 ch\u00e2n FB c\u0169ng t\u0103ng, IC s\u1ebd t\u1ef1 \u0111\u1ed9ng \u0111\u01b0a ra t\u00edn hi\u1ec7u \u0111i\u1ec1u \u00a0khi\u1ec3n gi\u1ea3m xu\u1ed1ng \u0111\u00e8n Mosfet ho\u1ea1t \u0111\u1ed9ng gi\u1ea3m v\u00e0 \u0111i\u1ec7n \u00e1p ra s\u1ebd gi\u1ea3m tr\u1edf v\u1ec1 v\u1ecb tr\u00ed ban \u0111\u1ea7u. N\u1ebfu \u0111i\u1ec7n \u00e1p ra b\u1ecb gi\u1ea3m th\u00ec qu\u00e1 tr\u00ecnh \u0111i\u1ec1u khi\u1ec3n s\u1ebd ng\u01b0\u1ee3c l\u1ea1i.<\/span><\/p>\n

\u2013 M\u1ea1ch c\u00f3 th\u1ec3 \u0111i\u1ec1u ch\u1ec9nh \u0111\u01b0\u1ee3c \u0111i\u1ec7n \u00e1p ra thay \u0111\u1ed5i t\u1eeb 1 \u0111\u1ebfn 3V \u00a0khi ta thay \u0111\u1ed5i gi\u00e1 tr\u1ecb \u0111i\u1ec7n tr\u1edf tr\u00ean c\u1ea7u ph\u00e2n \u00e1p R106-R107 t\u1ee9c l\u00e0 thay \u0111\u1ed5i \u0111i\u1ec7n \u00e1p h\u1ed3i ti\u1ebfp v\u1ec1 ch\u00e2n FB c\u1ee7a IC<\/span><\/p>\n

\"Ch\u00e2n
Ch\u00e2n IC v\u00e0 h\u00ecnh \u1ea3nh IC th\u1ef1c t\u1ebf<\/figcaption><\/figure>\n

 <\/p>\n

C\u00e1c c\u00e2u h\u1ecfi c\u1ee7a h\u1ecdc vi\u00ean v\u1ec1 m\u1ea1ch c\u1ea5p ngu\u1ed3n chipset<\/strong><\/h2>\n

Chipset nam hay h\u1ecfng d\u1ea1ng g\u00ec? Nguy\u00ean nh\u00e2n t\u1ea1i sao h\u1ecfng<\/h3>\n

Hai d\u1ea5u hi\u1ec7u cho th\u1ea5y chipset h\u1ecfng:<\/span><\/p>\n

– Ch\u1eadp chipset – ch\u1eadp \u0111\u01b0\u1eddng ngu\u1ed3n 3,3v v\u00e0 5v<\/span><\/p>\n

Nguy\u00ean nh\u00e2n do c\u1ea5p ngu\u1ed3n cho main khi ch\u01b0a b\u1eadt c\u00f4ng t\u1eafc chipset nam \u0111\u00e3 n\u00f3ng ho\u1eb7c sau khi b\u1eadt c\u00f4ng t\u1eafc, chipset r\u1ea5t n\u00f3ng (s\u1edd tay l\u00e2u c\u00f3 th\u1ec3 b\u1ecfng) \u0111\u00e2y l\u00e0 hi\u1ec7n t\u01b0\u1ee3ng chipset b\u1ecb ch\u1eadp, tr\u01b0\u1eddng h\u1ee3p n\u00e0y b\u1ea1n c\u1ea7n thay chipset nam.<\/span><\/p>\n

– Kh\u00f4ng ra t\u00edn hi\u1ec7u reset h\u1ec7 th\u1ed1ng:<\/span><\/p>\n

Reset h\u1ec7 th\u1ed1ng l\u00e0 t\u00edn hi\u1ec7u ph\u00e1t ra t\u1eeb chipset nam \u0111\u1ec3 ph\u00e1t ra t\u1eeb chipset nam \u0111\u1ec3 kh\u1edfi \u0111\u1ed9ng tr\u00ean c\u00e1c th\u00e0nh ph\u1ea7n mainboard. T\u00edn hi\u1ec7u reset h\u1ec7 th\u1ed1ng c\u00f3 th\u1ec3 ki\u1ec3m tra \u0111\u01b0\u1ee3c b\u1eb1ng card test main, n\u1ebfu b\u1ecb m\u1ea5t t\u00edn hi\u1ec7u reset h\u1ec7 th\u1ed1ng th\u00ec chipset b\u1eafc, CPU v\u00e0 c\u00e1c th\u00e0nh ph\u1ea7n kh\u00e1c nhau kh\u00f4ng th\u1ec3 ho\u1ea1t \u0111\u1ed9ng \u0111\u01b0\u1ee3c, v\u00ec v\u1eady mainboard s\u1ebd kh\u00f4ng kh\u1edfi \u0111\u1ed9ng, kh\u00f4ng b\u00e1o s\u1ef1 c\u1ed1, kh\u00f4ng l\u00ean m\u00e0n h\u00ecnh.<\/span><\/p>\n

N\u1ebfu h\u1ecfng c\u00e1c m\u1ea1ch \u1ed5n \u00e1p ngu\u1ed3n cho 2 chipset th\u00ec mainboard c\u00f3 hi\u1ec7n t\u01b0\u1ee3ng g\u00ec?<\/h3>\n

– N\u1ebfu m\u1ea1ch \u1ed5n \u00e1p cho Chipset kh\u00f4ng ho\u1ea1t \u0111\u1ed9ng (m\u1ea5t \u0111i\u1ec7n \u00e1p 1.5V ho\u1eb7c 1.8V c\u1ea5p cho hai chipset) hai chipset s\u1ebd kh\u00f4ng ho\u1ea1t \u0111\u1ed9ng, khi \u0111\u00f3 mainboard s\u1ebd kh\u00f4ng kh\u1edfi \u0111\u1ed9ng, kh\u00f4ng b\u00e1o s\u1ef1 c\u1ed1 b\u1eb1ng ti\u1ebfng b\u00edp, kh\u00f4ng l\u00ean m\u00e0n h\u00ecnh, tuy nhi\u00ean b\u1eadt m\u1edf ngu\u1ed3n v\u1eabn c\u00f3 t\u00e1c d\u1ee5ng qu\u1ea1t ngu\u1ed3n v\u1eabn quay.<\/span><\/p>\n

– B\u1ea1n ki\u1ec3m tra card test main b\u1ea1n s\u1ebd th\u1ea5y \u0111\u00e8n RST s\u00e1ng li\u00ean t\u1ee5c kh\u00f4ng t\u1eaft ho\u1eb7c kh\u00f4ng s\u00e1ng.<\/span><\/p>\n

– Tr\u01b0\u1eddng h\u1ee3p mosfet b\u1ecb ch\u1eadp => s\u1ebd \u0111\u01b0a c\u1ea3 3.3V ho\u1eb7c 5V v\u00e0o chipset. Khi \u0111\u00f3 chipset ch\u1ea1y b\u1ecb n\u00f3ng v\u00e0 s\u1ebd b\u1ecb h\u1ecfng sau m\u1ed9t th\u1eddi gian s\u1eed d\u1ee5ng.<\/span><\/p>\n

M\u1ecdi chi ti\u1ebft xin vui l\u00f2ng li\u00ean h\u1ec7:<\/i><\/p>\n

C\u00d4NG TY C\u1ed4 PH\u1ea6N H\u1eccC VI\u1ec6N IT<\/strong><\/p>\n

MST: 0108733789<\/strong><\/p>\n

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H\u1ecdc vi\u1ec7n IT.vn \u2013 Truy\u1ec1n ngh\u1ec1 th\u1ef1c t\u1ebf c\u00f9ng b\u1ea1n \u0111\u1ebfn th\u00e0nh c\u00f4ng!\u00a0<\/i><\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"

Nh\u01b0 b\u1ea1n \u0111\u00e3 bi\u1ebft tr\u00ean mainboard c\u00f3 3 ngu\u1ed3n \u1ed5n \u00e1p ch\u00ednh \u0111\u00f3 l\u00e0 VRM \u1ed5n \u00e1p ngu\u1ed3n cho CPU, ngu\u1ed3n RAM. So v\u1edbi c\u00e1ch x\u00e1c \u0111\u1ecbnh ngu\u1ed3n c\u1ea5p cho CPU v\u00e0 RAM th\u00ec c\u00e1ch ph\u00e2n t\u00edch m\u1ea1ch c\u1ea5p ngu\u1ed3n cho chipset kh\u00f3 h\u01a1n v\u00ec n\u00f3 ch\u1ee7 y\u1ebfu d\u1ef1a v\u00e0o kinh nghi\u1ec7m.<\/p>\n","protected":false},"author":95,"featured_media":8477,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[96,94],"tags":[282],"_links":{"self":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts\/8476"}],"collection":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/users\/95"}],"replies":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=8476"}],"version-history":[{"count":0,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts\/8476\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/media\/8477"}],"wp:attachment":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=8476"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=8476"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=8476"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}