{"id":30485,"date":"2024-05-11T17:24:46","date_gmt":"2024-05-11T10:24:46","guid":{"rendered":"https:\/\/hocvienit.vn\/?p=30485"},"modified":"2024-07-01T16:34:31","modified_gmt":"2024-07-01T09:34:31","slug":"socket-cpu-la-gi-tim-hieu-cac-loai-socket-cpu-chi-tiet","status":"publish","type":"post","link":"https:\/\/hocvienit.vn\/?p=30485","title":{"rendered":"Socket CPU l\u00e0 g\u00ec? T\u00ecm hi\u1ec3u c\u00e1c lo\u1ea1i Socket CPU chi ti\u1ebft"},"content":{"rendered":"

Nh\u1edd c\u00f3 Socket CPU th\u00ec CPU m\u1edbi c\u00f3 th\u1ec3 k\u1ebft n\u1ed1i v\u00e0 l\u00e0m vi\u1ec7c v\u1edbi mainboard c\u1ee7a m\u00e1y t\u00ednh. V\u1eady Socket CPU l\u00e0 g\u00ec m\u00e0 \u0111\u00f3ng vai quan tr\u1ecdng nh\u01b0 v\u1eady? C\u00f9ng H\u1ecdc vi\u1ec7n iT.vn t\u00ecm hi\u1ec3u v\u1ec1 ch\u1ee9c n\u0103ng c\u1ee7a CPU v\u00e0 c\u00e1c lo\u1ea1i socket CPU ph\u1ed5 bi\u1ebfn hi\u1ec7n nay nh\u00e9!<\/span><\/p>\n

\"Socket
Socket CPU l\u00e0 g\u00ec? T\u00ecm hi\u1ec3u c\u00e1c lo\u1ea1i Socket CPU chi ti\u1ebft<\/figcaption><\/figure>\n

1. Socket CPU l\u00e0 g\u00ec?<\/b><\/h2>\n

Theo <\/span>Wikipedia<\/span><\/a>, Socket CPU hay \u0110\u1ebf c\u1eafm CPU l\u00e0 ph\u1ea7n ch\u00e2n c\u1eafm ch\u1ee9a m\u1ed9t ho\u1eb7c nhi\u1ec1u th\u00e0nh ph\u1ea7n c\u01a1 kh\u00ed c\u00f3 nhi\u1ec7m v\u1ee5 k\u1ebft n\u1ed1i <\/span>CPU<\/span><\/a> v\u1edbi mainboard \u0111\u1ec3 truy\u1ec1n t\u1ea3i d\u1eef li\u1ec7u. \u0110\u1ebf c\u1eafm s\u1ebd gi\u00fap ng\u01b0\u1eddi d\u00f9ng d\u1ec5 d\u00e0ng th\u00e1o l\u1eafp, n\u00e2ng c\u1ea5p CPU, \u0111\u1ed3ng th\u1eddi c\u1ed1 \u0111\u1ecbnh v\u1ecb tr\u00ed CPU tr\u00e1nh b\u1ecb x\u00ea d\u1ecbch trong qu\u00e1 tr\u00ecnh s\u1eed d\u1ee5ng.<\/span><\/p>\n

M\u1ed7i lo\u1ea1i Socket CPU l\u1ea1i c\u00f3 h\u00ecnh d\u1ea1ng, k\u00edch th\u01b0\u1edbc, s\u1ed1 ch\u00e2n c\u1eafm v\u00e0 c\u00e1ch th\u1ee9c l\u1eafp \u0111\u1eb7t kh\u00e1c nhau n\u00ean s\u1ebd ch\u1ec9 t\u01b0\u01a1ng th\u00edch v\u1edbi d\u00f2ng CPU c\u1ee5 th\u1ec3. Ngo\u00e0i ra, c\u00e1c nh\u00e0 s\u1ea3n xu\u1ea5t laptop th\u01b0\u1eddng h\u00e0n CPU v\u00e0o socket \u0111\u1ec3 ti\u1ebft ki\u1ec7m kh\u00f4ng gian b\u00ean trong m\u00e1y. Do \u0111\u00f3, kh\u1ea3 n\u0103ng n\u00e2ng c\u1ea5p CPU tr\u00ean laptop r\u1ea5t h\u1ea1n ch\u1ebf.<\/span><\/p>\n

2. C\u00e1c lo\u1ea1i Socket CPU ph\u1ed5 bi\u1ebfn<\/b><\/h2>\n

Hi\u1ec7n nay c\u00f3 5 lo\u1ea1i Socket CPU ph\u1ed5 bi\u1ebfn tr\u00ean th\u1ecb tr\u01b0\u1eddng l\u00e0: PGA, rPGA, LGA, ZIF v\u00e0 BGA. Ch\u00fang ta c\u00f3 th\u1ec3 d\u1ec5 d\u00e0ng ph\u00e2n bi\u1ec7t c\u00e1c lo\u1ea1i \u0111\u1ebf c\u1eafm n\u00e0y d\u1ef1a v\u00e0o c\u00e1ch th\u1ee9c l\u1eafp \u0111\u1eb7t c\u1ee5 th\u1ec3 nh\u01b0 sau:<\/span><\/p>\n

2.1. Socket PGA (Pin Grid Array)<\/b><\/h3>\n
\"Socket
Socket PGA (Pin Grid Array)<\/figcaption><\/figure>\n

Socket PGA (Pin Grid Array) c\u00f3 ki\u1ec3u d\u00e1ng vu\u00f4ng, ch\u00e2n c\u1eafm CPU c\u1eafm v\u00e0o l\u1ed7 tr\u00ean socket v\u00e0 \u0111\u01b0\u1ee3c k\u1ebft n\u1ed1i b\u1eb1ng c\u00e1ch nh\u1ea5n nh\u1eb9 CPU xu\u1ed1ng. \u01afu \u0111i\u1ec3m c\u1ee7a socket PGA l\u00e0 d\u1ec5 d\u00e0ng th\u00e1o l\u1eafp CPU v\u00e0 gi\u00e1 th\u00e0nh r\u1ebb.<\/span><\/p>\n

Tuy nhi\u00ean, socket PGA c\u0169ng c\u00f3 nh\u01b0\u1ee3c \u0111i\u1ec3m l\u00e0 d\u1ec5 b\u1ecb h\u01b0 h\u1ea1i ch\u00e2n c\u1eafm CPU, chi\u1ebfm nhi\u1ec1u di\u1ec7n t\u00edch mainboard v\u00e0 kh\u00f3 kh\u0103n trong vi\u1ec7c v\u1ec7 sinh mainboard. Socket PGA t\u01b0\u01a1ng th\u00edch v\u1edbi CPU Intel Core th\u1ebf h\u1ec7 6 tr\u1edf xu\u1ed1ng v\u00e0 AMD Ryzen th\u1ebf h\u1ec7 1 v\u00e0 2.<\/span><\/p>\n

2.2. Socket rPGA (Reduced Pin Grid Array)<\/b><\/h3>\n
\"Socket
Socket rPGA (Reduced Pin Grid Array)<\/figcaption><\/figure>\n

Socket rPGA (Reduced Pin Grid Array) l\u00e0 phi\u00ean b\u1ea3n n\u00e2ng c\u1ea5p c\u1ee7a socket PGA truy\u1ec1n th\u1ed1ng, \u0111\u01b0\u1ee3c Intel gi\u1edbi thi\u1ec7u l\u1ea7n \u0111\u1ea7u ti\u00ean v\u1edbi socket G1 (rPGA 988A) c\u00f9ng d\u00f2ng CPU Core i3\/i5\/i7 th\u1ebf h\u1ec7 1.<\/span><\/p>\n

Socket rPGA c\u00f3 thi\u1ebft k\u1ebf nh\u1ecf g\u1ecdn h\u01a1n nh\u1edd gi\u1ea3m kho\u1ea3ng c\u00e1ch gi\u1eefa c\u00e1c ch\u00e2n c\u1eafm, \u0111\u1ed3ng th\u1eddi c\u1ea3i thi\u1ec7n hi\u1ec7u qu\u1ea3 t\u1ea3n nhi\u1ec7t v\u00e0 kh\u1ea3 n\u0103ng k\u1ebft n\u1ed1i.<\/span><\/p>\n

2.3. Socket ZIF (Zero Insertion Force)<\/b><\/h3>\n
\"Socket
Socket ZIF (Zero Insertion Force)<\/figcaption><\/figure>\n

Socket ZIF (Zero Insertion Force) l\u00e0 phi\u00ean b\u1ea3n n\u00e2ng c\u1ea5p c\u1ee7a socket PGA, c\u00f3 th\u00eam ch\u00e2n n\u1ed1i tr\u00ean CPU. Socket ZIF \u0111\u01b0\u1ee3c k\u1ebft n\u1ed1i b\u1eb1ng c\u00e1ch \u0111\u1eb7t CPU l\u00ean socket v\u00e0 kh\u00f3a l\u1ea1i b\u1eb1ng thanh \u0111\u00f2n b\u1ea9y.<\/span><\/p>\n

\u01afu \u0111i\u1ec3m c\u1ee7a socket ZIF l\u00e0 d\u1ec5 d\u00e0ng th\u00e1o l\u1eafp CPU v\u00e0 l\u1ef1c c\u1eafm CPU nh\u1eb9 nh\u00e0ng. Tuy nhi\u00ean, socket ZIF c\u0169ng c\u00f3 nh\u01b0\u1ee3c \u0111i\u1ec3m l\u00e0 \u00edt ph\u1ed5 bi\u1ebfn h\u01a1n c\u00e1c lo\u1ea1i socket kh\u00e1c v\u00e0 \u0111\u1ed9 b\u1ec1n th\u1ea5p h\u01a1n LGA. Socket ZIF t\u01b0\u01a1ng th\u00edch v\u1edbi CPU Intel Core th\u1ebf h\u1ec7 6 tr\u1edf xu\u1ed1ng.<\/span><\/p>\n

2.4. Socket LGA (Land Grid Array)<\/b><\/h3>\n
\"Socket
Socket LGA (Land Grid Array)<\/figcaption><\/figure>\n

Socket LGA (Land Grid Array) \u0111\u01b0\u1ee3c t\u00edch h\u1ee3p s\u1eb5n tr\u00ean mainboard, CPU c\u00f3 khe c\u1eafm t\u01b0\u01a1ng th\u00edch \u0111\u1ec3 g\u1eafn v\u00e0o. \u01afu \u0111i\u1ec3m c\u1ee7a socket LGA l\u00e0 \u0111\u1ed9 b\u1ec1n cao, ti\u1ebft ki\u1ec7m di\u1ec7n t\u00edch mainboard v\u00e0 d\u1ec5 d\u00e0ng v\u1ec7 sinh.<\/span><\/p>\n

Tuy nhi\u00ean, socket LGA c\u0169ng c\u00f3 nh\u01b0\u1ee3c \u0111i\u1ec3m l\u00e0 kh\u00f3 th\u00e1o l\u1eafp CPU h\u01a1n PGA v\u00e0 gi\u00e1 th\u00e0nh cao h\u01a1n. Socket LGA t\u01b0\u01a1ng th\u00edch v\u1edbi CPU Intel Core th\u1ebf h\u1ec7 7 tr\u1edf l\u00ean.<\/span><\/p>\n

2.5. Socket BGA (Ball Grid Array)<\/b><\/h3>\n
\"Socket
Socket BGA (Ball Grid Array)<\/figcaption><\/figure>\n

Socket BGA (Ball Grid Array) l\u00e0 phi\u00ean b\u1ea3n PGA v\u1edbi ch\u00e2n c\u1eafm v\u00e0 \u1ed5 c\u1eafm \u0111\u01b0\u1ee3c h\u00e0n v\u00e0o socket, gi\u00fap gi\u1ea3m thi\u1ec3u h\u01b0 h\u1ea1i ch\u00e2n c\u1eafm v\u00e0 CPU.<\/span><\/p>\n

\u01afu \u0111i\u1ec3m c\u1ee7a socket BGA l\u00e0 \u0111\u1ed9 b\u1ec1n cao. Tuy nhi\u00ean, socket BGA c\u0169ng c\u00f3 nh\u01b0\u1ee3c \u0111i\u1ec3m l\u00e0 kh\u00f3 th\u00e1o l\u1eafp CPU v\u00e0 gi\u00e1 th\u00e0nh cao. Socket BGA t\u01b0\u01a1ng th\u00edch v\u1edbi m\u1ed9t s\u1ed1 d\u00f2ng CPU Intel v\u00e0 AMD cao c\u1ea5p.<\/span><\/p>\n

3. S\u1ef1 t\u01b0\u01a1ng th\u00edch gi\u1eefa Socket v\u00e0 CPU<\/b><\/h2>\n

Khi c\u1ea7n n\u00e2ng c\u1ea5p CPU cho m\u00e1y t\u00ednh th\u00ec y\u1ebfu t\u1ed1 quan tr\u1ecdng l\u00e0 m\u1ee9c \u0111\u1ed9 t\u01b0\u01a1ng th\u00edch v\u1edbi socket. B\u1ea1n c\u1ea7n ch\u1ecdn CPU c\u00f3 k\u00edch th\u01b0\u1edbc ph\u00f9 h\u1ee3p v\u1edbi \u0111\u1ebf c\u1eafm v\u00e0 c\u00f3 s\u1ed1 l\u01b0\u1ee3ng ch\u00e2n ti\u1ebfp x\u00fac t\u01b0\u01a1ng th\u00edch. Ngo\u00e0i ra, b\u1ea1n c\u0169ng c\u1ea7n \u0111\u1ea3m b\u1ea3o r\u1eb1ng CPU h\u1ed7 tr\u1ee3 lo\u1ea1i socket c\u1ee7a mainboard.<\/span><\/p>\n

Nh\u1eefng th\u00f4ng tin v\u1ec1 CPU v\u00e0 lo\u1ea1i socket h\u1ed7 tr\u1ee3 th\u01b0\u1eddng \u0111\u01b0\u1ee3c c\u00e1c nh\u00e0 s\u1ea3n xu\u1ea5t ghi trong t\u00e0i li\u1ec7u \u0111i k\u00e8m ho\u1eb7c b\u1ea1n c\u00f3 th\u1ec3 truy c\u1eadp v\u00e0o website c\u1ee7a nh\u00e0 s\u1ea3n xu\u1ea5t \u0111\u1ec3 tra c\u1ee9u.<\/span><\/p>\n

Tr\u00ean \u0111\u00e2y l\u00e0 chia s\u1ebb c\u1ee7a H\u1ecdc vi\u1ec7n iT.vn v\u1ec1 \u0111\u1ebf c\u1eafm CPU. N\u1ebfu c\u00f3 b\u1ea5t c\u1ee9 th\u1eafc m\u1eafc n\u00e0o th\u00ec h\u00e3y \u0111\u1ec3 l\u1ea1i b\u00ecnh lu\u1eadn ngay b\u00ean d\u01b0\u1edbi b\u00e0i vi\u1ebft n\u00e0y ho\u1eb7c inbox tr\u1ef1c ti\u1ebfp cho H\u1ecdc vi\u1ec7n iT.vn \u0111\u1ec3 \u0111\u01b0\u1ee3c gi\u1ea3i \u0111\u00e1p t\u1ed1t nh\u1ea5t.<\/span><\/p>\n

M\u1ecdi chi ti\u1ebft xin vui l\u00f2ng li\u00ean h\u1ec7:
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\nH\u1ecdc vi\u1ec7n IT.vn \u2013 Truy\u1ec1n ngh\u1ec1 th\u1ef1c t\u1ebf c\u00f9ng b\u1ea1n \u0111\u1ebfn th\u00e0nh c\u00f4ng!\u00a0<\/i><\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"

Socket CPU l\u00e0 g\u00ec m\u00e0 \u0111\u00f3ng vai quan tr\u1ecdng nh\u01b0 v\u1eady? C\u00f9ng H\u1ecdc vi\u1ec7n iT.vn t\u00ecm hi\u1ec3u v\u1ec1 ch\u1ee9c n\u0103ng c\u1ee7a CPU v\u00e0 c\u00e1c lo\u1ea1i socket CPU ph\u1ed5 bi\u1ebfn hi\u1ec7n nay nh\u00e9!<\/p>\n","protected":false},"author":95,"featured_media":30486,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[95,94],"tags":[],"_links":{"self":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts\/30485"}],"collection":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/users\/95"}],"replies":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=30485"}],"version-history":[{"count":0,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts\/30485\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/media\/30486"}],"wp:attachment":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=30485"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=30485"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=30485"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}