{"id":1538,"date":"2018-07-06T04:41:02","date_gmt":"2018-07-06T04:41:02","guid":{"rendered":"https:\/\/hocvienit.vn\/?p=1538"},"modified":"2024-12-09T14:40:50","modified_gmt":"2024-12-09T07:40:50","slug":"ach-nguon-cpu-vrm-vol-regu-module","status":"publish","type":"post","link":"https:\/\/hocvienit.vn\/?p=1538","title":{"rendered":"M\u1ea1ch ngu\u1ed3n CPU (VRM – Vol Regu Module)"},"content":{"rendered":"
<\/header>\n
\n
\n
\n
\"M\u1ea1ch
M\u1ea1ch ngu\u1ed3n CPU<\/figcaption><\/figure>\n

V\u1ecb tr\u00ed c\u1ee7a m\u1ea1ch VRM tr\u00ean Mainboard<\/strong><\/span>
\nVRM l\u00e0 g\u00ec? – VRM l\u00e0 (Vol Regu Module – Modun \u1ed5n \u00e1p) – M\u1ea1ch \u1ed5n \u00e1p ngu\u1ed3n cho CPU<\/span>
\n– M\u1ea1ch VRM (\u1ed5n \u00e1p ngu\u1ed3n cho CPU) th\u01b0\u1eddng n\u1eb1m b\u00ean c\u1ea1nh Socket c\u1ee7a CPU, m\u1ea1ch bao g\u1ed3m c\u00e1c th\u00e0nh ph\u1ea7n:<\/span><\/p>\n

\"\"<\/span><\/p>\n

– IC dao \u0111\u1ed9ng (hay c\u00f2n g\u1ecdi l\u00e0 IC \u0111i\u1ec1u xung )<\/span>
\n– IC \u0111\u1ea3o pha (hay c\u00f2n g\u1ecdi l\u00e0 driver, l\u00e1i xung)<\/span>
\n– C\u00e1c \u0111\u00e8n Mosfet<\/span>
\n– C\u00e1c cu\u1ed9n d\u00e2y (d\u1ec5 nh\u1eadn bi\u1ebft g\u1ed3m c\u00e1c cu\u1ed9n d\u00e2y \u0111\u1ed3ng to xung quanh socket g\u1eafn CPU)<\/span>
\n– C\u00e1c t\u1ee5 l\u1ecdc (to v\u00e0 nhi\u1ec1u xung quanh CPU )<\/span>
\nCh\u1ee9c n\u0103ng c\u1ee7a m\u1ea1ch VRM<\/strong>\u00a0l\u00e0 \u0111i\u1ec1u khi\u1ec3n ngu\u1ed3n c\u1ea5p cho CPU \u0111\u01b0\u1ee3c \u1ed5n \u0111\u1ecbnh v\u1edbi m\u1ed9t d\u00f2ng \u0111i\u1ec7n t\u01b0\u01a1ng \u0111\u1ed1i l\u1edbn kho\u1ea3ng 8 \u0111\u1ebfn 10A<\/span><\/p>\n

B\u1ea1n \u0111\u01b0a tr\u1ecf chu\u1ed9t v\u00e0o s\u01a1 \u0111\u1ed3 \u0111\u1ec3 xem ch\u00fa th\u00edch<\/em><\/span><\/p>\n

M\u1ea1ch VRM tr\u00ean Mainboard ASUS Socket 478<\/em><\/span><\/p>\n

B\u1ea1n \u0111\u01b0a tr\u1ecf chu\u1ed9t v\u00e0o s\u01a1 \u0111\u1ed3 \u0111\u1ec3 xem ch\u00fa th\u00edch
\n<\/em>\"\"<\/span>
\nM\u1ea1ch VRM tr\u00ean Mainboard GIGABYTE Socket 775<\/em><\/span>
\n\"\"<\/span><\/p>\n

\"\"<\/span>
\nM\u1ea1ch VRM tr\u00ean Mainboard GIGABYTE Socket 478<\/em><\/span><\/p>\n

    \n
  1. \n
      \n
    1. S\u01a1 \u0111\u1ed3 nguy\u00ean l\u00fd c\u1ee7a m\u1ea1ch VRM tr\u00ean Mainboard<\/strong><\/span>2.1\u00a0– C\u00e1c th\u00e0nh ph\u1ea7n ch\u00ednh c\u1ee7a m\u1ea1ch VRM<\/strong><\/span>
      \n–\u00a0IC dao \u0111\u1ed9ng\u00a0– c\u00f3 ch\u1ee9c n\u0103ng t\u1ea1o dao \u0111\u1ed9ng (t\u1ea1o xung PWM – xung \u0111i\u1ec1u ch\u1ebf \u0111\u1ed9 r\u1ed9ng) \u0111\u1ec3 \u0111i\u1ec1u khi\u1ec3n c\u00e1c c\u1eb7p \u0111\u00e8n Mosfet ho\u1ea1t \u0111\u1ed9ng<\/span>
      \n–\u00a0IC \u0111\u1ea3o pha\u00a0– t\u00e1ch m\u1ed7i dao \u0111\u1ed9ng ra th\u00e0nh 2 dao \u0111\u1ed9ng c\u00f3 pha ng\u01b0\u1ee3c nhau<\/span>
      \n–\u00a0C\u00e1c \u0111\u00e8n Mosfet\u00a0– Ho\u1ea1t \u0111\u1ed9ng \u0111\u00f3ng ng\u1eaft theo t\u00edn hi\u1ec7u \u0111i\u1ec1u khi\u1ec3n c\u1ee7a xung PWM, khi xung PWM c\u00f3 pha d\u01b0\u01a1ng th\u00ec Mosfet d\u1eabn, khi xung PWM c\u00f3 pha \u00e2m th\u00ec Mosfet ng\u1eaft.<\/span>
      \n–\u00a0Cu\u1ed9n d\u00e2y\u00a0– k\u1ebft h\u1ee3p v\u1edbi t\u1ee5 \u0111i\u1ec7n \u0111\u1ec3 l\u1ecdc \u0111i\u1ec7n \u00e1p xung th\u00e0nh \u00e1p m\u1ed9t chi\u1ec1u DC<\/span>
      \n–\u00a0T\u1ee5 \u0111i\u1ec7n\u00a0– k\u1ebft h\u1ee3p v\u1edbi cu\u1ed9n d\u00e2y \u0111\u1ec3 l\u1ecdc \u0111i\u1ec7n \u00e1p xung th\u00e0nh \u00e1p m\u1ed9t chi\u1ec1u DC<\/span>2.2\u00a0– Nguy\u00ean l\u00fd ho\u1ea1t \u0111\u1ed9ng c\u1ee7a m\u1ea1ch VRM:<\/strong><\/span>
      \n– Khi c\u00f3 \u0111i\u1ec7n \u00e1p Vcc cung c\u1ea5p cho IC dao \u0111\u1ed9ng (ISL 6565A) \u0111\u1ed3ng th\u1eddi ch\u00e2n PGOOD (ch\u00e2n b\u00e1o s\u1ef1 c\u1ed1 ngu\u1ed3n ATX) c\u00f3 \u0111i\u1ec7n \u00e1p b\u00ecnh tu\u1eddng th\u00ec IC s\u1ebd ho\u1ea1t \u0111\u1ed9ng, n\u00f3 t\u1ea1o ra c\u00e1c xung PWM1, PWM2 v\u00e0 PWM3 \u0111\u1ec3 c\u1ea5p cho 3 c\u1eb7p \u0111\u00e8n Mosfet<\/span>
      \n– C\u00e1c xung PWM \u0111\u01b0\u1ee3c t\u00e1ch ra l\u00e0m hai xung c\u00f3 pha ng\u01b0\u1ee3c nhau khi \u0111i qua IC \u0111\u1ea3o pha, sau \u0111\u00f3 hai xung ng\u01b0\u1ee3c pha s\u1ebd \u0111\u01b0a \u0111\u1ebfn \u0111i\u1ec1u khi\u1ec3n ch\u00e2n G c\u1ee7a c\u00e1c \u0111\u00e8n Mosfet.<\/span>
      \n– Khi \u0111\u00e8n Mosfet c\u00f3 xung d\u01b0\u01a1ng \u0111i\u1ec1u khi\u1ec3n n\u00f3 s\u1ebd d\u1eabn, c\u00f3 xung \u00e2m \u0111i\u1ec1u khi\u1ec3n n\u00f3 s\u1ebd ng\u1eaft, v\u00ec v\u1eady \u0111\u00e8n Mosfet s\u1ebd \u0111\u00f3ng ng\u1eaft li\u00ean t\u1ee5c theo nh\u1ecbp dao \u0111\u1ed9ng c\u1ee7a xung PWM<\/span>
      \n– Hai \u0111\u00e8n Mosfet tr\u00ean m\u1ed7i c\u1eb7p s\u1ebd \u0111\u00f3ng ng\u1eaft lu\u00e2n phi\u00ean, \u0111\u00e8n n\u00e0y d\u1eabn th\u00ec \u0111\u00e8n kia ng\u1eaft v\u00e0 ng\u01b0\u1ee3c l\u1ea1i, t\u1ea1o ra \u0111i\u1ec7n \u00e1p xung \u1edf \u0111i\u1ec3m gi\u1eefa.<\/span>
      \n– Sau \u0111\u00f3 \u0111i\u1ec7n \u00e1p xung s\u1ebd \u0111\u01b0\u1ee3c m\u1ea1ch l\u1ecdc L – C l\u1ecdc th\u00e0nh \u0111i\u1ec7n \u00e1p m\u1ed9t chi\u1ec1u b\u1eb1ng ph\u1eb3ng \u0111\u1ec3 c\u1ea5p cho CPU<\/span>
      \n
      \n<\/strong>2.3 –\u00a0\u0110\u1eb7c \u0111i\u1ec3m<\/strong>c\u1ee7a m\u1ea1ch VRM\u00a0<\/strong><\/span>
      \n– M\u1ea1ch bi\u1ebfn \u0111\u1ed5i \u0111\u01b0\u1ee3c \u0111i\u1ec7n \u00e1p v\u00e0o t\u1eeb 12V xu\u1ed1ng kho\u1ea3ng 1,5V v\u00e0 t\u0103ng d\u00f2ng t\u1eeb 2A l\u00ean kho\u1ea3ng 8 \u0111\u1ebfn 10A<\/span>
      \n– B\u1ea3n th\u00e2n m\u1ea1ch c\u00f3 c\u00f4ng su\u1ea5t t\u1ed5n hao nh\u1ecf ch\u1ec9 chi\u1ebfm kho\u1ea3ng 20% c\u00f4ng su\u1ea5t hi\u1ec7u d\u1ee5ng.<\/span>
      \n– M\u1ea1ch c\u00f3 kh\u1ea3 n\u0103ng t\u1ef1 \u0111\u1ed9ng \u0111i\u1ec1u ch\u1ec9nh \u0111i\u1ec7n \u00e1p c\u1ea5p cho CPU th\u00f4ng qua t\u00edn hi\u1ec7u Logic \u1edf c\u00e1c ch\u00e2n VID0, VID1, VID2,<\/span>
      \nVID3, VID4 t\u1eeb CPU b\u00e1o v\u1ec1.<\/span>
      \n–\u00a0Tr\u00ean c\u00e1c Mainboard Pentium 4 khi kh\u00f4ng g\u1eafn CPU th\u00ec c\u00e1c ch\u00e2n VID c\u00f3 gi\u00e1 tr\u1ecb logic 1 v\u00e0 m\u1ea1ch VRM \u0111\u01b0a ra \u0111i\u1ec7n \u00e1p
      \nm\u1eb7c \u0111\u1ecbnh b\u1eb1ng 0V<\/strong><\/em>\u00a0(l\u01b0u \u00fd r\u1ea5t qua tr\u1ecdng)<\/span>
      \n– \u0110i\u1ec7n \u00e1p \u0111\u1ea7u v\u00e0o c\u1ee7a m\u1ea1ch VRM tr\u00ean c\u00e1c Mainboard Pen 4 l\u00e0 12V, tr\u00ean c\u00e1c Mainboard Pen 3 l\u00e0 5V<\/span>
      \n– \u0110i\u1ec7n \u00e1p ra c\u1ee7a m\u1ea1ch VRM tr\u00ean c\u00e1c Mainboard Pen 3 khi kh\u00f4ng g\u1eafn CPU l\u00e0 kho\u1ea3ng 1,6V<\/span>\"\"<\/span>S\u01a1 \u0111\u1ed3 nguy\u00ean l\u00fd m\u1ea1ch VRM (\u1ed5n \u00e1p ngu\u1ed3n cho CPU)<\/em><\/span>Ch\u00fa th\u00edch c\u00e1c ch\u00e2n c\u1ee7a IC dao \u0111\u1ed9ng:<\/strong><\/span>
      \n– VCC – Ngu\u1ed3n cung c\u1ea5p cho IC<\/span>
      \n– PWM1, PWM2, PWM3 – C\u00e1c ch\u00e2n xung \u0111i\u1ec1u ch\u1ebf \u0111\u1ed9 r\u1ed9ng \u0111\u01b0a \u0111\u1ebfn \u0111\u1ec3 \u0111i\u1ec1u khi\u1ec3n c\u00e1c c\u1eb7p \u0111\u00e8n Mosfet<\/span>
      \n– ISEN1, ISEN2, ISEN3 c\u00e1c ch\u00e2n c\u1ea3m bi\u1ebfn v\u1ec1 d\u00f2ng \u0111i\u1ec7n<\/span>
      \n– EN – Ch\u00e2n cho ph\u00e9p IC ho\u1ea1t \u0111\u1ed9ng<\/span>
      \n– ENLL (ch\u00e2n PGOOD) – Ch\u00e2n b\u00e1o tr\u1ea1ng th\u00e1i ngu\u1ed3n ATX ho\u1ea1t \u0111\u1ed9ng t\u1ed1t<\/span>
      \n– C\u00e1c ch\u00e2n VID0, VID1, VID2, VID3, VID4 b\u00e1o tr\u1ea1ng th\u00e1i Logic cho bi\u1ebft gi\u00e1 tr\u1ecb \u0111i\u1ec7n \u00e1p m\u00e0 CPU s\u1eed d\u1ee5ng<\/span>
      \n– PGOOD , OVP – b\u00e1o t\u00ecnh tr\u1ea1ng c\u1ee7a m\u1ea1ch VRM v\u1ec1 chipset nam<\/span>
      \n– VSEN – Ch\u00e2n c\u1ea3m bi\u1ebfn \u0111i\u1ec7n \u00e1p (ch\u00e2n h\u1ed3i ti\u1ebfp)<\/span>\"\"<\/span><\/li>\n<\/ol>\n<\/li>\n<\/ol>\n
        \n
      1. \n
          \n
        1. M\u1ea1ch VRM tr\u00ean Mainboard MSI\"\"<\/strong>M\u1ea1ch \u1ed5n \u00e1p VRM tr\u00ean Mainboard MSI<\/em><\/span><\/li>\n<\/ol>\n<\/li>\n<\/ol>\n
            \n
          1. \n
              \n
            1. S\u1ef1 gi\u1ed1ng v\u00e0 kh\u00e1c nhau c\u1ee7a m\u1ea1ch VRM gi\u1eefa Mainboard Pentium 4 v\u00e0 Petium 3<\/strong><\/span>
              \n– Nguy\u00ean l\u00fd ho\u1ea1t \u0111\u1ed9ng c\u1ee7a m\u1ea1ch VRM tr\u00ean hai lo\u1ea1i Mainboard l\u00e0 nh\u01b0 nhau<\/span>
              \n– \u0110i\u1ec3m kh\u00e1c nhau c\u01a1 b\u1ea3n c\u1ee7a m\u1ea1ch VRM gi\u1eefa hai lo\u1ea1i Main l\u00e0 \u0111i\u1ec7n \u00e1p \u0111\u1ea7u v\u00e0o c\u1ee7a Mainboard Pen 3 s\u1eed d\u1ee5ng 5V c\u00f2n \u0111i\u1ec7n \u00e1p \u0111\u1ea7u v\u00e0o c\u1ee7a Mainboard Pen 4 s\u1eed d\u1ee5ng 12V<\/span>
              \n– Khi kh\u00f4ng g\u1eafn CPU th\u00ec m\u1ea1ch VRM c\u1ee7a Mainboard Pen 3 ra \u0111i\u1ec7n \u00e1p m\u1eb7c \u0111\u1ecbnh l\u00e0 1,6V c\u00f2n m\u1ea1ch VRM c\u1ee7a Mainboard Pen 4 ra m\u1eb7c \u0111\u1ecbnh s\u1ea5p s\u1ec9 0V<\/span>\"\"<\/span>
              \nMainboard Pentium 3 ch\u1ec9 c\u00f3 m\u1ed9t c\u1eb7p \u0111\u00e8n Mosfet tr\u00ean m\u1ea1ch VRM<\/em><\/span><\/li>\n<\/ol>\n<\/li>\n<\/ol>\n
                \n
              1. \n
                  \n
                1. M\u1ea1ch b\u00e1o s\u1ef1 c\u1ed1 c\u1ee7a m\u1ea1ch VRM v\u1ec1 Chipset nam<\/strong><\/span>
                  \n– Khi m\u1ea1ch VRM ho\u1ea1t \u0111\u1ed9ng t\u1ed1t s\u1ebd cho t\u00edn hi\u1ec7u VRM_GD b\u00e1o v\u1ec1 Chipset nam cho bi\u1ebft t\u00ecnh tr\u1ea1ng ho\u1ea1t \u0111\u1ed9ng c\u1ee7a m\u1ea1ch \u1ed5n \u00e1p cho CPU \u0111\u00e3 t\u1ed1t, CPU \u0111\u00e3 s\u1eb5n s\u00e0ng h\u1ecdt \u0111\u1ed9ng.<\/span>
                  \n– T\u00edn hi\u1ec7u VRM_GD \u0111\u01b0a v\u1ec1 Chipset l\u00e0 m\u1ed9t \u0111i\u1ec1u ki\u1ec7n \u0111\u1ec3 Chipset nam \u0111\u01b0a ra t\u00edn hi\u1ec7u Reset h\u1ec7 th\u1ed1ng, n\u1ebfu m\u1ea1ch VRM kh\u00f4ng ho\u1ea1t \u0111\u1ed9ng ho\u1eb7c c\u00f3 s\u1ef1 c\u1ed1, t\u00edn hi\u1ec7u VRM_GD s\u1ebd kh\u00f4ng c\u00f3 v\u00ec v\u1eady m\u00e0 Chipset s\u1ebd kh\u00f4ng cho ra t\u00edn hi\u1ec7u Reset \u0111\u1ec3 kh\u1edfi \u0111\u1ed9ng m\u00e1y.<\/span>\"\"<\/span><\/li>\n<\/ol>\n<\/li>\n<\/ol>\n
                    \n
                  1. \n
                      \n
                    1. Ph\u01b0\u01a1ng ph\u00e1p ki\u1ec3m tra m\u1ea1ch VRM – Ki\u1ec3m tra ngu\u1ed3n c\u1ea5p cho CPU<\/strong><\/span>
                      \nKhi ki\u1ec3m tra \u0111i\u1ec7n \u00e1p c\u1ea5p cho CPU, b\u1ea1n c\u1ea7n l\u01b0u \u00fd m\u1ea5y \u0111i\u1ec3m sau \u0111\u00e2y:<\/span>
                      \n– V\u1edbi Mainboard Pentium 3 b\u1ea1n c\u00f3 th\u1ec3 \u0111o ki\u1ec3m tra \u0111i\u1ec7n \u00e1p VCORE c\u1ea5p cho CPU m\u00e0 kh\u00f4ng c\u1ea7n g\u1eafn CPU v\u00e0o Socket<\/span>
                      \n– V\u1edbi c\u00e1c Mainboard Pentium 4 \u0111\u1ec3 \u0111o \u0111i\u1ec7n \u00e1p c\u1ea5p cho CPU, b\u1ea1n c\u1ea7n g\u1eafn CPU v\u00e0o Socket tr\u01b0\u1edbc khi \u0111o, n\u1ebfu kh\u00f4ng c\u00f3 CPU th\u00ec m\u1ea1ch VRM c\u1ee7a Main Pen 4 ra \u0111i\u1ec7n \u00e1p m\u1eb7c \u0111\u1ecbnh b\u1eb1ng 0V.<\/span>
                      \n– Tr\u01b0\u1edbc khi g\u1eafn CPU v\u00e0o Socket \u0111\u1ec3 ki\u1ec3m tra \u0111i\u1ec7n \u00e1p, b\u1ea1n c\u1ea7n \u0111o \u0111i\u1ec7n \u00e1p VCORE tr\u01b0\u1edbc (khi kh\u00f4ng c\u00f3 CPU) \u0111\u1ec3 lo\u1ea1i tr\u1eeb tr\u01b0\u1eddng h\u1ee3p m\u1ea1ch VRM b\u1ecb ch\u1eadp Mosfet l\u00e0m \u0111i\u1ec7n \u00e1p VCORE t\u0103ng cao g\u00e2y h\u1ecfng CPU c\u1ee7a b\u1ea1n.<\/span>6.1 –\u00a0V\u1ecb tr\u00ed \u0111o \u0111i\u1ec7n \u00e1p VCORE (VCORE l\u00e0 ngu\u1ed3n ra c\u1ee7a VRM c\u1ea5p cho CPU)<\/strong><\/span>
                      \n– B\u1ea1n h\u00e3y \u0111o \u0111i\u1ec7n \u00e1p VCORE (\u0111i\u1ec7n \u00e1p c\u1ea5p cho CPU) \u0111o v\u00e0o \u0111\u1ea7u c\u00e1c cu\u1ed9n d\u00e2y ra b\u1eb1ng thang DC, b\u1ea1n c\u00f3 th\u1ec3 \u0111o v\u00e0o c\u1ea3 hai \u0111\u1ea7u cu\u1ed9n d\u00e2y \u0111\u1ec1u \u0111\u01b0\u1ee3c, n\u1ebfu \u0111\u1ed3ng h\u1ed3 b\u00e1o kho\u1ea3ng 1,5V DC l\u00e0 m\u1ea1ch VRM \u0111\u00e3 “OK”, n\u1ebfu \u0111\u1ed3ng h\u1ed3 b\u00e1o \u0111i\u1ec7n \u00e1p b\u1eb1ng 0 ho\u1eb7c d\u01b0\u1edbi 1V DC l\u00e0 m\u1ea1ch VRM b\u1ecb h\u1ecfng.<\/span><\/p>\n
                      \"\u0110o
                      \u0110o \u0111i\u1ec7n \u00e1p c\u1ea5p cho CPU<\/figcaption><\/figure>\n

                      6.2\u00a0– C\u00e1c b\u01b0\u1edbc ki\u1ec3m tra m\u1ea1ch VRM v\u00e0 \u0111i\u1ec7n \u00e1p VCORE tr\u00ean Mainboard Pentium 4<\/strong><\/span><\/p>\n

                      B\u01b0\u1edbc 1<\/strong>\u00a0– \u0110o \u0111i\u1ec7n \u00e1p VCORE khi ch\u01b0a g\u1eafn CPU ph\u1ea3i c\u00f3 \u0111i\u1ec7n \u00e1p s\u1ea5p s\u1ec9 b\u1eb1ng 0V, n\u1ebfu \u0111i\u1ec7n \u00e1p VCORE khi ch\u01b0a g\u1eafn CPU \u0111\u00e3 c\u00f3 12V l\u00e0 m\u1ea1ch VRM b\u1ecb ch\u1eadp Mosfet ph\u00eda tr\u00ean (Mosfet c\u00f3 ch\u00e2n D \u0111\u1ea5u v\u00e0o 12V)<\/span><\/p>\n

                      B\u01b0\u1edbc 2<\/strong>\u00a0– G\u1eafn CPU v\u00e0o, c\u1ea5p ngu\u1ed3n, b\u1eadt c\u00f4ng t\u1eafc v\u00e0 \u0111o l\u1ea1i \u0111i\u1ec7n \u00e1p VCORE \u1edf ch\u00e2n cu\u1ed9n d\u00e2y ra<\/span>
                      \n– N\u1ebfu c\u00f3 \u0111i\u1ec7n \u00e1p ra kho\u1ea3ng 1,5V l\u00e0 m\u1ea1ch VRM t\u1ed1t<\/span>
                      \n– N\u1ebfu kh\u00f4ng c\u00f3 \u0111i\u1ec7n \u00e1p ra ho\u1eb7c ra th\u1ea5p d\u01b0\u1edbi 1V l\u00e0 m\u1ea1ch VRM h\u1ecfng<\/span><\/p>\n

                      Gi\u1ea3i th\u00edch c\u00e1c b\u01b0\u1edbc \u0111o ki\u1ec3m tra \u1edf tr\u00ean:<\/strong><\/span><\/p>\n

                      B\u01b0\u1edbc 1\u00a0(B\u1eadt ngu\u1ed3n v\u00e0 \u0111o khi ch\u01b0a c\u00f3 CPU)<\/strong><\/span>
                      \n– B\u1ea1n c\u1ea5p ngu\u1ed3n cho Mainboard, ch\u1ec9nh \u0111\u1ed3ng h\u1ed3 \u1edf thang 10V DC \u0111\u1ec3 chu\u1ea9n b\u1ecb \u0111o \u0111i\u1ec7n \u00e1p VCORE \u1edf \u0111\u1ea7u cu\u1ed9n d\u00e2y ra c\u1ee7a m\u1ea1ch \u1ed5n \u00e1p VRM<\/span>
                      \n– G\u1eafn Card Test Main \u0111\u1ec3 quan s\u00e1t tr\u1ea1ng th\u00e1i c\u1ee7a ngu\u1ed3n<\/span>
                      \n– B\u1eadt c\u00f4ng t\u1eafc (ch\u1eadp hai ch\u00e2n PWR) \u0111\u1ec3 cho ngu\u1ed3n ch\u00ednh ch\u1ea1y, c\u00e1c \u0111\u00e8n 3,3V, 5V v\u00e0 12V tr\u00ean Card Test s\u00e1ng l\u00ean l\u00e0 ngu\u1ed3n ATX t\u1ed1t v\u00e0 Mainboard kh\u00f4ng b\u1ecb ch\u1eadp<\/span>
                      \n– \u0110o v\u00e0o ch\u00e2n cu\u1ed9n d\u00e2y \u0111i\u1ec7n \u00e1p ph\u1ea3i s\u1ea5p s\u1ec9 b\u1eb1ng 0 V (v\u00ec ch\u01b0a g\u1eafn CPU n\u00ean m\u1ea1ch VRM cho ra \u0111i\u1ec7n \u00e1p m\u1eb7c \u0111\u1ecbnh = 0V)<\/span>
                      \n=>\u00a0N\u1ebfu ch\u01b0a g\u1eafn CPU m\u00e0 \u0111o th\u1ea5y \u00e1p \u1edf \u0111\u1ea7u cu\u1ed9n d\u00e2y kho\u1ea3ng 5 \u0111\u1ebfn 10V<\/strong>\u00a0l\u00e0 m\u1ea1ch VRM \u0111ang b\u1ecb ch\u1eadp Mosfet, b\u1ea1n c\u1ea7n ki\u1ec3m tra k\u1ef9 c\u00e1c \u0111\u00e8n Mosfet.<\/span><\/p>\n

                      B\u01b0\u1edbc 2\u00a0(B\u1eadt ngu\u1ed3n v\u00e0 \u0111o khi \u0111\u00e3 g\u1eafn CPU v\u00e0o Socket tr\u00ean Main)<\/strong><\/span>
                      \n– G\u1eafn CPU v\u00e0o Socket tr\u00ean Mainboard (Ch\u1eafc ch\u1eafn l\u00e0 CPU t\u1ed1t)<\/span>
                      \n– B\u1ea1n c\u1ea5p ngu\u1ed3n cho Mainboard, ch\u1ec9nh \u0111\u1ed3ng h\u1ed3 \u1edf thang 10V DC \u0111\u1ec3 chu\u1ea9n b\u1ecb \u0111o \u0111i\u1ec7n \u00e1p VCORE \u1edf \u0111\u1ea7u cu\u1ed9n d\u00e2y ra c\u1ee7a m\u1ea1ch \u1ed5n \u00e1p VRM<\/span>
                      \n– G\u1eafn Card Test Main \u0111\u1ec3 quan s\u00e1t tr\u1ea1ng th\u00e1i c\u1ee7a ngu\u1ed3n<\/span>
                      \n– B\u1eadt c\u00f4ng t\u1eafc (ch\u1eadp hai ch\u00e2n PWR) \u0111\u1ec3 cho ngu\u1ed3n ch\u00ednh ch\u1ea1y, c\u00e1c \u0111\u00e8n 3,3V, 5V v\u00e0 12V tr\u00ean Card Test s\u00e1ng l\u00ean l\u00e0 ngu\u1ed3n ATX t\u1ed1t v\u00e0 Mainboard kh\u00f4ng b\u1ecb ch\u1eadp<\/span>
                      \n– \u0110o v\u00e0o ch\u00e2n cu\u1ed9n d\u00e2y \u0111i\u1ec7n \u00e1p ph\u1ea3i l\u00ean kho\u1ea3ng 1,5V (v\u00ec khi \u0111\u00e3 g\u1eafn CPU => m\u1ea1ch VRM ph\u1ea3i cho ra \u0111i\u1ec7n \u00e1p kho\u1ea3ng 1,5V hay b\u1eb1ng \u0111i\u1ec7n \u00e1p c\u1ee7a CPU s\u1eed d\u1ee5ng)<\/span>
                      \n=>\u00a0N\u1ebfu \u0111\u00e3 g\u1eafn CPU m\u00e0 \u0111o th\u1ea5y \u00e1p \u1edf \u0111\u1ea7u cu\u1ed9n d\u00e2y (\u00e1p VCORE) v\u1eabn b\u1eb1ng 0V l\u00e0 m\u1ea1ch VRM kh\u00f4ng ho\u1ea1t \u0111\u1ed9ng<\/strong><\/span>
                      \nB\u1ea1n c\u1ea7n s\u1eeda ch\u1eefa nh\u01b0 sau:<\/span>
                      \n– Kh\u00f2 l\u1ea1i ch\u00e2n IC dao \u0111\u1ed9ng t\u1ea1o xung PWM v\u00e0 IC \u0111\u1ea3o pha<\/span>
                      \n– Ki\u1ec3m tra xem c\u00f3 \u0111\u00e8n Mosfet n\u00e0o b\u1ecb ch\u1eadp kh\u00f4ng ?<\/span>
                      \n– Thay IC dao \u0111\u1ed9ng t\u1ea1o xung PWM<\/span><\/li>\n<\/ol>\n<\/li>\n<\/ol>\n<\/div>\n

                      B\u00e0n th\u1ea3o c\u1ee7a D\u1ea1y Ngh\u1ec1 H\u00e0 N\u1ed9i:\u00a0<\/strong><\/span><\/p>\n

                      – B\u00e0i n\u00e0y \u0111\u1ed1i v\u1edbi c\u00e1c b\u1ea1n m\u1edbi v\u00e0o ngh\u1ec1 th\u00ec c\u1ef1c k\u1ef3 kh\u00f3 kh\u0103n do kh\u00f4ng n\u1eafm r\u1ecf “nguy\u00ean l\u00fd h\u1ecdat \u0111\u1ed9ng” c\u1ee7a m\u1ea1ch. Nh\u01b0ng \u0111\u1ed1i v\u1edbi d\u00e2n th\u1ee3 “\u0111i\u1ec7n t\u1eed” th\u00ec n\u00f3 kh\u00e1 \u0111\u01a1n gi\u1ea3n v\u00ec ch\u1ec9 l\u00e0 m\u1ea1ch “\u1ed5n \u00e1p \u0111i\u1ec1u xung” b\u00ecnh th\u01b0\u1eddng. D\u1ea1ng \u1ed5n \u00e1p \u0111i\u1ec1u xung n\u00e0y n\u1ebfu c\u00e1c b\u1ea1n h\u1ecdc qua Tivi hay monitor th\u00ec n\u00f3 ph\u1ee9c t\u1ea1p h\u01a1n nhi\u1ec1u. Trong Tivi hay Monitor CRT m\u1ea1ch “\u1ed5n \u00e1p \u0111i\u1ec1u xung” ngu\u1ed3n ch\u00ednh ph\u1ea3i l\u1ea5y t\u00ednh hi\u1ec7u “phi h\u1ed3i” t\u1eeb “bi\u1ebfn th\u1ebf Cao \u00e1p” v\u1ec1… Nh\u01b0ng trong m\u1ea1ch n\u00e0y ch\u1ec9 \u0111\u01a1n gi\u1ea3n c\u00f3 xung, c\u00f3 ngu\u1ed3n c\u1ea5p l\u00e0 c\u00f3 \u0111i\u1ec7n \u00e1p ng\u1ecf ra. N\u1ebfu CPU t\u1ed1t s\u1ebd c\u00f3 “h\u1ed3i ti\u1ebfp” VID0, VID1, VID2, VID3, VID4 v\u1ec1 m\u1ea1ch ti\u1ebfp t\u1ee5c h\u1ecdat \u0111\u1ed9ng, n\u1ebfu CPU kh\u00f4ng t\u1ed1t (kh\u00f4ng ti\u1ebfp x\u00fac t\u1ed1t ho\u1eb7c CPU ch\u1ebft) th\u00ec ng\u01b0ng c\u1ea5p xung --> ng\u1eaft ng\u1ecf ra.<\/span><\/p>\n

                      – N\u1ebfu m\u1ea5t ngu\u1ed3n c\u1ea5p cho CPU: ki\u1ec3m tra ng\u01b0\u1ee3c t\u1eeb CPU (ch\u1eafc r\u1eb1ng CPU t\u1ed1t) ti\u1ebfp x\u00fac CPU v\u1edbi socket t\u1ed1t, c\u00e1c MOSFET t\u1ed1t (kh\u00f4ng ch\u1ea1m, \u0111\u1ee9t, r\u00f2 r\u0129…) IC driver t\u1ed1t (\u0111o b\u1eb1ng m\u00e1y hi\u1ec7n s\u00f3ng ho\u1eb7c thay th\u1eed) IC \u0111i\u1ec1u xung t\u1ed1t (\u0111o b\u1eb1ng m\u00e1y hi\u1ec7n s\u00f3ng ho\u1eb7c thay th\u1eed).<\/span><\/p>\n

                      – M\u1ea1ch n\u00e0y n\u1ebfu d\u00e2n “\u0111i\u1ec7n t\u1eed” c\u00f3 kinh nghi\u1ec7m d\u1ec3 d\u00e0ng kh\u00e1m ph\u00e1 ra b\u1eb1ng c\u00e1ch v\u00e0o\u00a0https:\/\/www.alldatasheet.com<\/a>\u00a0\u0111\u1ec3 tra th\u00f4ng tinh v\u1ec1 c\u00e1c IC \u0111i\u1ec1u xung l\u00e0 s\u1ebd c\u00f3 m\u1ed9t b\u00e0i ph\u00e2n t\u00edch nguy\u00ean l\u00fd ho\u1ea1t \u0111\u1ed9ng r\u1ea5t chi ti\u1ebft. D\u0129 nhi\u00ean l\u00e0 b\u1eb1ng ti\u1ebfng anh r\u1ed3i. C\u00e1c b\u1ea1n t\u1ef1 kh\u00e1m ph\u00e1 th\u00eam t\u1eeb g\u1ee3i \u00fd n\u00e0y nh\u00e9. D\u00e2n ph\u1ea7n c\u1ee9ng m\u00e0 kh\u00f4ng bi\u1ebft x\u00e0i\u00a0https:\/\/www.alldatasheet.com<\/a>\u00a0th\u00ec ch\u1ec9 l\u00e0 d\u00e2n “th\u00e1o l\u1eafp” th\u00f4i.<\/span><\/p>\n

                      – Do m\u1ea1ch n\u00e0y h\u1ecdat \u0111\u1ed9ng v\u1edbi d\u00f2ng r\u1ea5t cao n\u00ean x\u00e1c xu\u1ea5t h\u01b0 h\u1ecfng \u1edf khu v\u1ef1c n\u00e0y l\u00e0 r\u1ea5t l\u1edbn. N\u1eafm r\u1ecf nguy\u00ean l\u00fd v\u00e0 s\u1eeda \u0111\u01b0\u1ee3c m\u1ea1ch n\u00e0y l\u00e0 th\u00e0nh c\u00f4ng 60-70%<\/span><\/p>\n

                      – S\u1edbm nh\u1eadn th\u1ea5y y\u1ebfu t\u1ed1 quan tr\u1ecdng c\u1ee7a m\u1ea1ch n\u00e0y n\u00ean ri\u00eang \u00a0\u0111\u00e3 c\u00f3 m\u1ed9t b\u00e0i vi\u1ebft c\u00f9ng ch\u1ee7 \u0111\u1ec1 nh\u01b0ng b\u1eb1ng c\u00e1ch ti\u1ebfp nh\u1eadn v\u00e0 tr\u00ecnh b\u00e0y kh\u00e1c h\u01a1n. M\u1ecdi ng\u01b0\u1eddi tham kh\u1ea3o th\u00eam.<\/span><\/p>\n

                      * Nh\u1eafc l\u1ea1i:<\/strong>\u00a0B\u00e0i vi\u1ebft n\u00e0y\u00a0\u00a0s\u01b0u t\u1ea7m t\u1eeb hocnghe.com tuy nhi\u00ean \u0111i\u1ec3m kh\u00e1c bi\u1ec7t khi b\u1ea1n xem b\u00e0i vi\u1ebft \u1edf\u00a0https:\/\/daynghehanoi.com<\/a>\u00a0l\u00e0 kh\u00f4ng c\u1ea7n \u0111\u0103ng k\u00fd, \u0111\u0103ng nh\u1eadp hay t\u1ed1n b\u1ea5t k\u1ef3 chi ph\u00ed n\u00e0o. Ngo\u00e0i ra b\u1ea1n c\u0169ng c\u00f3 th\u1ec3 download t\u00e0i li\u1ec7u to\u00e0n t\u1eadp v\u1ec1 \u0111\u1ec3 ti\u1ec7n tham kh\u1ea3o. Th\u00eam n\u1eefa, c\u00e1c th\u1eafc m\u1eafc li\u00ean quan b\u1ea1n c\u00f3 th\u1ec3 comments v\u00e0 s\u1ebd nh\u1eadn \u0111\u01b0\u1ee3c \u0111\u00e1p h\u1ed3i trong th\u1eddi gian s\u1edbm nh\u1ea5t c\u00f3 th\u1ec3.<\/span><\/p>\n<\/div>\n

                      M\u1ecdi chi ti\u1ebft xin vui l\u00f2ng li\u00ean h\u1ec7:<\/i><\/p>\n

                      C\u00d4NG TY C\u1ed4 PH\u1ea6N H\u1eccC VI\u1ec6N IT<\/strong>
                      \nMST: 0108733789<\/strong>
                      \nT\u1ed5ng \u0111\u00e0i h\u1ed7 tr\u1ee3: 024 3566 8686 \u2013 Hotline: 0981 223 001<\/strong>
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                      \u0110\u0103ng k\u00fd k\u00eanh Youtube \u0111\u1ec3 theo d\u00f5i c\u00e1c b\u00e0i h\u1ecdc c\u1ee7a Hu\u1ea5n luy\u1ec7n vi\u00ean t\u1ed1t nh\u1ea5t:<\/strong>\u00a0http:\/\/bit.ly\/Youtube_HOCVIENiT<\/a><\/p>\n

                      Tham gia c\u1ed9ng \u0111\u1ed3ng H\u1ecdc vi\u1ec7n IT.vn t\u1ea1i:<\/strong>\u00a0https:\/\/www.facebook.com\/groups\/www.hocvienit.vn\/<\/a><\/p>\n

                      Tr\u1ee5 s\u1edf H\u00e0 N\u1ed9i:<\/strong>\u00a0S\u1ed1 8 ng\u00f5 117 Th\u00e1i H\u00e0, \u0110\u1ed1ng \u0110a, H\u00e0 N\u1ed9i<\/p>\n

                      H\u1ed3 Ch\u00ed Minh:<\/strong>\u00a0S\u1ed1 283\/45 C\u00e1ch M\u1ea1ng Th\u00e1ng T\u00e1m, Ph\u01b0\u1eddng 12, Qu\u1eadn 10,\u00a0TP.HCM
                      \nH\u1ea3i Ph\u00f2ng:<\/strong>\u00a0S\u1ed1 94 Qu\u00e1n Nam, L\u00ea Ch\u00e2n, H\u1ea3i Ph\u00f2ng<\/p>\n

                      Th\u00e1i Nguy\u00ean:<\/strong>\u00a0S\u1ed1 297 L\u01b0\u01a1ng Ng\u1ecdc Quy\u1ebfn, TP. Th\u00e1i Nguy\u00ean
                      \nH\u1ecdc vi\u1ec7n IT.vn \u2013 Truy\u1ec1n ngh\u1ec1 th\u1ef1c t\u1ebf c\u00f9ng b\u1ea1n \u0111\u1ebfn th\u00e0nh c\u00f4ng!\u00a0<\/i><\/strong><\/p>\n

                       <\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

                      V\u1ecb tr\u00ed c\u1ee7a m\u1ea1ch VRM tr\u00ean Mainboard VRM l\u00e0 g\u00ec? – VRM l\u00e0 (Vol Regu Module – Modun \u1ed5n \u00e1p) – M\u1ea1ch \u1ed5n \u00e1p ngu\u1ed3n cho CPU – M\u1ea1ch VRM (\u1ed5n \u00e1p ngu\u1ed3n cho CPU) th\u01b0\u1eddng n\u1eb1m b\u00ean c\u1ea1nh Socket c\u1ee7a CPU, m\u1ea1ch bao g\u1ed3m c\u00e1c th\u00e0nh ph\u1ea7n: – IC dao \u0111\u1ed9ng (hay c\u00f2n g\u1ecdi […]\n","protected":false},"author":95,"featured_media":1540,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[734],"tags":[366,240,686],"_links":{"self":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts\/1538"}],"collection":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/users\/95"}],"replies":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1538"}],"version-history":[{"count":0,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts\/1538\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/media\/1540"}],"wp:attachment":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1538"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1538"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1538"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}