{"id":1524,"date":"2018-07-06T04:27:27","date_gmt":"2018-07-06T04:27:27","guid":{"rendered":"https:\/\/hocvienit.vn\/?p=1524"},"modified":"2025-01-08T16:44:43","modified_gmt":"2025-01-08T09:44:43","slug":"nguon-thu-cap-tren-laptop","status":"publish","type":"post","link":"https:\/\/hocvienit.vn\/?p=1524","title":{"rendered":"Ngu\u1ed3n th\u1ee9 c\u1ea5p tr\u00ean laptop"},"content":{"rendered":"
<\/header>\n
\n
\"Ngu\u1ed3n
<\/span> Ngu\u1ed3n th\u1ee9 c\u1ea5p tr\u00ean laptop<\/span><\/figcaption><\/figure>\n

1 – Kh\u00e1i ni\u1ec7m v\u00e0 \u0111\u1eb7c \u0111i\u1ec3m c\u1ee7a ngu\u1ed3n th\u1ee9 c\u1ea5p<\/strong><\/span><\/h2>\n
    \n
  • Ngu\u1ed3n th\u1ee9 c\u1ea5p l\u00e0 ngu\u1ed3n \u0111i\u1ec7n xu\u1ea5t hi\u1ec7n sau khi ta b\u1ea5m c\u00f4ng t\u1eafc m\u1edf ngu\u1ed3n.<\/span><\/li>\n
  • Ngu\u1ed3n th\u1ee9 c\u1ea5p bao g\u1ed3m to\u00e0n b\u1ed9 c\u00e1c \u0111i\u1ec7n \u00e1p cung c\u1ea5p cho c\u00e1c b\u1ed9 ph\u1eadn c\u1ee7a m\u00e1y \u0111\u1ec3 chu\u1ea9n b\u1ecb \u0111\u01b0a m\u00e1y v\u00e0o ch\u1ebf \u0111\u1ed9 ho\u1ea1t \u0111\u1ed9ng.<\/span>
    \n(kh\u00f4ng t\u00ednh ngu\u1ed3n VCORE c\u1ea5p cho CPU).<\/span><\/li>\n
  • C\u00e1c \u0111i\u1ec7n \u00e1p th\u1ee9 c\u1ea5p 5V v\u00e0 3,3V s\u1eed d\u1ee5ng \u0111i\u1ec7n \u00e1p c\u1ea5p tr\u01b0\u1edbc 5V v\u00e0 3,3V v\u00e0 \u0111\u00f3ng qua c\u00e1c chuy\u1ec3n m\u1ea1ch \u0111i\u1ec7n t\u1eed d\u01b0\u1edbi s\u1ef1 \u0111i\u1ec1u<\/span>
    \nkhi\u1ec3n c\u1ee7a l\u1ec7nh m\u1edf ngu\u1ed3n th\u1ee9 c\u1ea5p.<\/span><\/li>\n
  • C\u00e1c \u0111i\u1ec7n \u00e1p kh\u00e1c \u0111\u01b0\u1ee3c t\u1ea1o ra b\u1edfi c\u00e1c ngu\u1ed3n xung nh\u01b0 \u0111i\u1ec7n \u00e1p: 2,5V – 1,8V – 1,5V – 1,25V – 1,2V – 1,05V – 0,9V (trong \u0111\u00f3\u00a0<\/span>
    \n\u0111i\u1ec7n \u00e1p 2,5V v\u00e0 1,25V c\u1ea5p cho DDR, \u0111i\u1ec7n \u00e1p 1,8V v\u00e0 0,9V c\u1ea5p cho DDR2)<\/span><\/li>\n
  • C\u00e1c ngu\u1ed3n th\u1ee9 c\u1ea5p ch\u1ec9 xu\u1ea5t hi\u1ec7n khi m\u00e1y \u0111\u00e3 c\u00f3 ngu\u1ed3n c\u1ea5p tr\u01b0\u1edbc.<\/span><\/li>\n<\/ul>\n

    2 – S\u01a1 \u0111\u1ed3 t\u1ed5ng qu\u00e1t v\u1ec1 c\u00e1c ngu\u1ed3n th\u1ee9 c\u1ea5p<\/strong><\/span><\/h2>\n
    \"S\u01a1
    <\/span> S\u01a1 \u0111\u1ed3 t\u1ed5ng qu\u00e1t v\u1ec1 c\u00e1c ngu\u1ed3n th\u1ee9 c\u1ea5p<\/span><\/figcaption><\/figure>\n
    \"S\u01a1
    <\/span> S\u01a1 \u0111\u1ed3 t\u1ed5ng qu\u00e1t v\u1ec1 c\u00e1c ngu\u1ed3n th\u1ee9 c\u1ea5p<\/span><\/figcaption><\/figure>\n
      \n
    • Khi c\u1ea5p ngu\u1ed3n DC-IN ho\u1eb7c g\u1eafn Pin v\u00e0o m\u00e1y.<\/span><\/li>\n<\/ul>\n

      => Ban \u0111\u1ea7u m\u00e1y c\u00f3 ngu\u1ed3n \u0111\u1ea7u v\u00e0o.<\/span><\/p>\n

        \n
      • Sau \u0111\u00f3 \u0111i\u1ec7n \u00e1p \u0111i qua m\u1ea1ch REGU \u0111\u1ec3 t\u1ea1o ra ngu\u1ed3n ch\u1edd c\u1ea5p cho IC \u0111i\u1ec1u khi\u1ec3n ngu\u1ed3n.<\/span><\/li>\n
      • N\u1ebfu ta s\u1eed d\u1ee5ng ngu\u1ed3n DC-IN s\u1ebd c\u00f3 t\u00edn hi\u1ec7u EXT_PWR (3) b\u00e1o v\u1ec1 IC \u0111i\u1ec1u khi\u1ec3n v\u00e0 IC s\u1ebd \u0111\u01b0a ra l\u1ec7nh m\u1edf ngu\u1ed3n c\u1ea5p tr\u01b0\u1edbc \u1edf b\u01b0\u1edbc (4).<\/span><\/li>\n
      • C\u00e1c ngu\u1ed3n xung ho\u1ea1t \u0111\u1ed9ng v\u00e0 t\u1ea1o ra c\u00e1c \u0111i\u1ec7n \u00e1p c\u1ea5p tr\u01b0\u1edbc 5v v\u00e0 3.3v.<\/span><\/li>\n
      • Khi ngu\u1ed3n c\u1ea5p tr\u01b0\u1edbc ho\u1ea1t \u0111\u1ed9ng, c\u00f3 t\u00edn hi\u1ec7u \u201cNgu\u1ed3n c\u1ea5p tr\u01b0\u1edbc b\u00e1o t\u1ed1t\u201d b\u00e1o v\u1ec1 IC \u0111i\u1ec1u khi\u1ec3n.<\/span><\/li>\n
      • Khi ta b\u1ea5m c\u00f4ng t\u1eafc, n\u1ebfu \u0111\u00e3 c\u00f3 t\u00edn hi\u1ec7u b\u00e1o \u201cNgu\u1ed3n c\u1ea5p tr\u01b0\u1edbc t\u1ed1t\u201d th\u00ec IC \u0111i\u1ec1u khi\u1ec3n m\u1edbi cho ra \u201cL\u1ec7nh m\u1edf ngu\u1ed3n th\u1ee9 c\u1ea5p 1\u201d v\u00e0 \u201cL\u1ec7nh m\u1edf ngu\u1ed3n th\u1ee9 c\u1ea5p 2\u201d.<\/span><\/li>\n
      • L\u1ec7nh 1 \u0111i\u1ec1u khi\u1ec3n cho c\u00e1c m\u1ea1ch c\u00f4ng t\u1eafc \u0111\u00f3ng \u0111\u1ec3 t\u1ea1o ra \u0111i\u1ec7n \u00e1p 5v v\u00e0 3.3v th\u1ee9 c\u1ea5p.<\/span><\/li>\n
      • \u0110\u1ed3ng th\u1eddi l\u1ec7nh 1 v\u00e0 l\u1ec7nh 2 \u0111i \u0111\u1ebfn \u0111i\u1ec1u khi\u1ec3n c\u00e1c ngu\u1ed3n xung t\u1ea1o ra c\u00e1c \u0111i\u1ec7n \u00e1p th\u1ee9 c\u1ea5p.<\/span><\/li>\n<\/ul>\n

        C\u00e1c ngu\u1ed3n \u0111i\u1ec7n v\u00e0 t\u1ea3i ti\u00eau th\u1ee5:<\/strong><\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
        C\u00e1c ngu\u1ed3n \u0111i\u1ec7n<\/strong><\/span><\/td>\nT\u1ea3i ti\u00eau th\u1ee5<\/strong><\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 5V c\u1ea5p tr\u01b0\u1edbc<\/span><\/td>\nChipset nam, c\u00e1c IC dao \u0111\u1ed9ng c\u1ee7a ngu\u1ed3n th\u1ee9 c\u1ea5p<\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 3,3V c\u1ea5p tr\u01b0\u1edbc<\/span><\/td>\nIC \u0111i\u1ec1u khi\u1ec3n ngu\u1ed3n \u0111\u1ec3 \u0111i\u1ec1u khi\u1ec3n m\u1ea1ch x\u1ea1c pin<\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 5V th\u1ee9 c\u1ea5p<\/span><\/td>\nC\u00e1c \u1ed5 \u0111\u0129a HDD, CDROM, m\u00e0n h\u00ecnh LCD, c\u00e1c c\u1ed5ng USB.<\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 3,3V th\u1ee9 c\u1ea5p<\/span><\/td>\nChipset nam, Clock Gen, SIO, BIOS, Sound, Net, Card Wifi<\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 2,5V th\u1ee9 c\u1ea5p<\/span><\/td>\nB\u1ed9 nh\u1edb DDR v\u00e0 Chipset b\u1eafc.<\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 1,8V th\u1ee9 c\u1ea5p<\/span><\/td>\nChip Video v\u00e0 b\u1ed9 nh\u1edb DDR2, Chipset b\u1eafc.<\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 1,5V th\u1ee9 c\u1ea5p<\/span><\/td>\nC\u1ea5p cho Chipset nam v\u00e0 Chipset b\u1eafc.<\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 1,25V th\u1ee9 c\u1ea5p (VTT)<\/span><\/td>\nC\u1ea5p ngu\u1ed3n ph\u1ee5 cho DDR<\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 1,2V th\u1ee9 c\u1ea5p<\/span><\/td>\nC\u1ea5p ngu\u1ed3n ph\u1ee5 cho hai Chipset<\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 1,05V (VIO) th\u1ee9 c\u1ea5p<\/span><\/td>\nC\u1ea5p ngu\u1ed3n ph\u1ee5 cho CPU.<\/span><\/td>\n<\/tr>\n
        Ngu\u1ed3n 0,9V (VTT)<\/span><\/td>\nC\u1ea5p ngu\u1ed3n ph\u1ee5 cho DDR2<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        3 – Nguy\u00ean l\u00fd c\u1ee7a c\u00e1c ngu\u1ed3n xung t\u1ea1o \u0111i\u1ec7n \u00e1p th\u1ee9 c\u1ea5p<\/strong><\/span><\/h2>\n
        \"Nguy\u00ean
        <\/span> Nguy\u00ean l\u00fd c\u1ee7a c\u00e1c ngu\u1ed3n xung t\u1ea1o \u0111i\u1ec7n \u00e1p th\u1ee9 c\u1ea5p<\/span><\/figcaption><\/figure>\n
        \"Nguy\u00ean
        <\/span> Nguy\u00ean l\u00fd c\u1ee7a c\u00e1c ngu\u1ed3n xung t\u1ea1o \u0111i\u1ec7n \u00e1p th\u1ee9 c\u1ea5p<\/span><\/figcaption><\/figure>\n
          \n
        • C\u00e1c ngu\u1ed3n xung t\u1ea1o ra \u0111i\u1ec7n \u00e1p th\u1ee9 c\u1ea5p \u0111\u1ec1u c\u00f3 c\u1ea5u t\u1ea1o gi\u1ed1ng nhau ch\u00fang ch\u1ec9 kh\u00e1ch nhau v\u1ec1 m\u1ea1ch h\u1ed3i ti\u1ebfp, t\u1eeb \u0111\u00f3 d\u1eabn \u0111\u1ebfn \u0111i\u1ec7n \u00e1p ra kh\u00e1c nhau.<\/span><\/li>\n
        • Khi m\u00e1y c\u00f3 ngu\u1ed3n \u0111\u1ea7u v\u00e0o, ch\u00e2n V+ \u0111\u01b0\u1ee3c cung c\u1ea5p 19v, t\u1ea7ng c\u00f4ng su\u1ea5t c\u0169ng \u0111\u01b0\u1ee3ng cung c\u1ea5p \u0111i\u1ec7n \u00e1p nh\u01b0 tr\u00ean.<\/span><\/li>\n
        • Khi m\u00e1y c\u00f3 ngu\u1ed3n c\u1ea5p tr\u01b0\u1edbc, c\u00e1c ch\u00e2n VDD v\u00e0 VCC\u00a0 \u0111\u01b0\u1ee3c cung c\u1ea5p \u0111i\u1ec7n \u00e1p 5v, \u0111\u1ed3ng th\u1eddi ch\u00e2n TON \u0111\u01b0\u1ee3c n\u1ed1i \u0111\u1ebfn 5v \u0111\u1ec3 cho ph\u00e9p IC ho\u1ea1t \u0111\u1ed9ng.<\/span><\/li>\n<\/ul>\n

          Khi c\u00f3 l\u1ec7nh m\u1edf ngu\u1ed3n th\u1ee9 c\u1ea5p, ch\u00e2n ON1 v\u00e0 ON2 c\u00f3 m\u1ee9c cao cho ph\u00e9p v\u1ebf 1 v\u00e0 v\u1ebf 2 c\u1ee7a IC ho\u1ea1t \u0111\u1ed9ng.<\/span><\/p>\n

            \n
          • V\u1ebf 1 cho \u0111i\u1ec7n \u00e1p ra t\u1ed1i \u0111a l\u00e0 2.5v (khi ch\u00e2n FB1) \u0111\u1ea5u mass.<\/span><\/li>\n
          • V\u1ebf 2 cho \u0111i\u1ec7n \u00e1p ra t\u1ed1i \u0111a l\u00e0 1.8V khi ch\u00e2n FB2 \u0111\u1ea5u mass.<\/span><\/li>\n
          • T\u00f9y theo gi\u00e1 tr\u1ecb c\u1ee7a \u0111i\u1ec7n tr\u1edf h\u1ed3i ti\u1ebfp m\u00e0 \u0111i\u1ec7n \u00e1p rat hay \u0111\u1ed5i.<\/span><\/li>\n
          • Khi ngu\u1ed3n ho\u1ea1t \u0111\u1ed9ng t\u1ed1t ch\u00e2n PGOOD s\u1ebd c\u00f3 m\u1ee9c cao b\u00e1o v\u1ec1 IC \u0111i\u1ec1u khi\u1ec3n cho bi\u1ebft m\u1ea1ch \u0111\u00e3 ho\u1ea1t \u0111\u1ed9ng t\u1ed1t.<\/span><\/li>\n<\/ul>\n

            Ch\u00fa th\u00edch c\u00e1c ch\u00e2n c\u1ee7a IC dao \u0111\u1ed9ng ngu\u1ed3n th\u1ee9 c\u1ea5p MAX 1715:<\/strong><\/span><\/p>\n\n\n\n\n\n<\/colgroup>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
            S\u1ed1 Pin<\/strong><\/span><\/td>\nK\u00fd hi\u1ec7u<\/strong><\/span><\/td>\nT\u00ean \u0111\u1ea7y \u0111\u1ee7<\/strong><\/span><\/td>\nCh\u1ee9c n\u0103ng<\/strong><\/span><\/td>\n<\/tr>\n
            1<\/span><\/td>\nOUT1<\/span><\/td>\nOutput<\/span><\/td>\nCh\u00e2n n\u1ed1i v\u1edbi \u0111i\u1ec7n \u00e1p ra v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            2<\/span><\/td>\nFB1<\/span><\/td>\nFeed Back<\/span><\/td>\nCh\u00e2n nh\u1eadn \u0111i\u1ec7n \u00e1p h\u1ed3i ti\u1ebfp \u0111\u1ec3 \u1ed5n \u0111\u1ecbnh \u00e1p ra v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            3<\/span><\/td>\nILIM1<\/span><\/td>\n<\/td>\nGi\u1edbi h\u1ea1n d\u00f2ng \u0111i\u1ec7n v\u1ebf 1 (b\u1ea3o v\u1ec7 qu\u00e1 d\u00f2ng)<\/span><\/td>\n<\/tr>\n
            4<\/span><\/td>\nV+<\/span><\/td>\n<\/td>\nCh\u00e2n ngu\u1ed3n c\u1ea5p V+ (t\u1eeb 5 \u0111\u1ebfn 24V)<\/span><\/td>\n<\/tr>\n
            5<\/span><\/td>\nTON<\/span><\/td>\n<\/td>\nCh\u00e2n cho ph\u00e9p IC ho\u1ea1t \u0111\u1ed9ng<\/span><\/td>\n<\/tr>\n
            6<\/span><\/td>\nSKIP<\/span><\/td>\n<\/td>\nCh\u00e2n ghim \u0111i\u1ec7n \u00e1p.<\/span><\/td>\n<\/tr>\n
            7<\/span><\/td>\nPGOOD<\/span><\/td>\nPower Good<\/span><\/td>\nB\u00e1o m\u1ee9c “1” khi ngu\u1ed3n ch\u1ea1y t\u1ed1t<\/span><\/td>\n<\/tr>\n
            8<\/span><\/td>\nAGND<\/span><\/td>\nAnalog GND<\/span><\/td>\nCh\u00e2n ti\u1ebfp Mass cho m\u1ea1ch Analog<\/span><\/td>\n<\/tr>\n
            9<\/span><\/td>\nREF<\/span><\/td>\nVref<\/span><\/td>\nCh\u00e2n ra \u0111i\u1ec7n \u00e1p chu\u1ea9n.<\/span><\/td>\n<\/tr>\n
            10<\/span><\/td>\nON1<\/span><\/td>\n<\/td>\nL\u1ec7nh \u0111i\u1ec1u khi\u1ec3n v\u1ebf 1 ho\u1ea1t \u0111\u1ed9ng<\/span><\/td>\n<\/tr>\n
            11<\/span><\/td>\nON2<\/span><\/td>\n<\/td>\nL\u1ec7nh \u0111i\u1ec1u khi\u1ec3n v\u1ebf 2 ho\u1ea1t \u0111\u1ed9ng<\/span><\/td>\n<\/tr>\n
            12<\/span><\/td>\nILIM2<\/span><\/td>\n<\/td>\nGi\u1edbi h\u1ea1n d\u00f2ng \u0111i\u1ec7n v\u1ebf 2 (b\u1ea3o v\u1ec7 qu\u00e1 d\u00f2ng)<\/span><\/td>\n<\/tr>\n
            13<\/span><\/td>\nFB2<\/span><\/td>\nFeed Back<\/span><\/td>\nCh\u00e2n nh\u1eadn \u0111i\u1ec7n \u00e1p h\u1ed3i ti\u1ebfp \u0111\u1ec3 \u1ed5n \u0111\u1ecbnh \u00e1p ra v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            14<\/span><\/td>\nOUT2<\/span><\/td>\n<\/td>\nN\u1ed1i v\u1edbi \u0111i\u1ec7n \u00e1p ra v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            15<\/span><\/td>\nNC1<\/span><\/td>\nNo Conect<\/span><\/td>\nKh\u00f4ng k\u1ebft n\u1ed1i<\/span><\/td>\n<\/tr>\n
            16<\/span><\/td>\nLX2<\/span><\/td>\n<\/td>\nCh\u00e2n n\u1ed1i v\u1edbi \u0111i\u1ec3m gi\u1eefa hai Mosfet v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            17<\/span><\/td>\nDH2<\/span><\/td>\nDrive High<\/span><\/td>\nCh\u00e2n dao \u0111\u1ed9ng ra \u0111i\u1ec7n m\u1ee9c cao v\u1ebf th\u1ee9 2<\/span><\/td>\n<\/tr>\n
            18<\/span><\/td>\nBST2<\/span><\/td>\nBOOST<\/span><\/td>\nCh\u00e2n t\u0103ng \u0111i\u1ec7n \u00e1p cho m\u1ea1ch OP Amply trong IC v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            19<\/span><\/td>\nDL2<\/span><\/td>\nDrive Low<\/span><\/td>\nCh\u00e2n dao \u0111\u1ed9ng ra m\u1ee9c th\u1ea5p v\u1ebf th\u1ee9 2<\/span><\/td>\n<\/tr>\n
            20<\/span><\/td>\nVDD<\/span><\/td>\n<\/td>\nCh\u00e2n ngu\u1ed3n c\u1ea5p 5V cho c\u00e1c m\u1ea1ch s\u1ed1<\/span><\/td>\n<\/tr>\n
            21<\/span><\/td>\nVCC<\/span><\/td>\n<\/td>\nCh\u00e2n c\u1ea5p ngu\u1ed3n 5V cho m\u1ea1ch t\u1ea1o dao \u0111\u1ed9ng<\/span><\/td>\n<\/tr>\n
            22<\/span><\/td>\nPGND<\/span><\/td>\n<\/td>\nCh\u00e2n ti\u1ebfp mass<\/span><\/td>\n<\/tr>\n
            23<\/span><\/td>\nNC2<\/span><\/td>\nNo Conect<\/span><\/td>\nKh\u00f4ng k\u1ebft n\u1ed1i<\/span><\/td>\n<\/tr>\n
            24<\/span><\/td>\nDL1<\/span><\/td>\nDrive Low<\/span><\/td>\nCh\u00e2n dao \u0111\u1ed9ng ra m\u1ee9c th\u1ea5p v\u1ebf th\u1ee9 1<\/span><\/td>\n<\/tr>\n
            25<\/span><\/td>\nBST1<\/span><\/td>\nBOOST<\/span><\/td>\nCh\u00e2n t\u0103ng \u0111i\u1ec7n \u00e1p cho m\u1ea1ch OP Amply trong IC v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            26<\/span><\/td>\nDH1<\/span><\/td>\nDrive High<\/span><\/td>\nCh\u00e2n dao \u0111\u1ed9ng ra \u0111i\u1ec7n m\u1ee9c cao v\u1ebf th\u1ee9 1<\/span><\/td>\n<\/tr>\n
            27<\/span><\/td>\nLX1<\/span><\/td>\n<\/td>\nCh\u00e2n n\u1ed1i v\u1edbi \u0111i\u1ec3m gi\u1eefa hai Mosfet v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            28<\/span><\/td>\nNC3<\/span><\/td>\nNo Conect<\/span><\/td>\nKh\u00f4ng k\u1ebft n\u1ed1i.<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

            C\u00e1c d\u00f2ng m\u00e0u \u0111\u1ecf l\u00e0 c\u00e1c ch\u00e2n \u0111\u1ea7u v\u00e0o quan tr\u1ecdng m\u00e0 ch\u00fang ta c\u1ea7n ki\u1ec3m tra khi m\u1ea1ch kh\u00f4ng ho\u1ea1t \u0111\u1ed9ng.<\/span><\/p>\n

            \"T\u00e1c
            <\/span> T\u00e1c d\u1ee5ng c\u1ee7a c\u00e1c ch\u00e2n BST, DH v\u00e0 LX<\/span><\/figcaption><\/figure>\n

            So s\u00e1nh c\u00e1c ch\u00e2n gi\u1eefa IC dao \u0111\u1ed9ng c\u1ee7a ngu\u1ed3n c\u1ea5p tr\u01b0\u1edbc v\u00e0 ngu\u1ed3n th\u1ee9 c\u1ea5p.<\/strong><\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
            \n

            IC dao \u0111\u1ed9ng ngu\u1ed3n<\/span><\/strong>
            \n<\/strong>c\u1ea5p tr\u01b0\u1edbc MAX 1631<\/span><\/strong><\/span><\/p>\n<\/td>\n

            		\n

            IC dao \u0111\u1ed9ng ngu\u1ed3n
            \nth\u1ee9 c\u1ea5p MAX 1715<\/strong><\/span><\/p>\n<\/td>\n

            		\n

            Ch\u1ee9c n\u0103ng<\/strong><\/span><\/p>\n<\/td>\n<\/tr>\n

            \n

            C\u00e1c ch\u00e2n<\/span>
            \ngi\u1ed1ng nhau<\/span><\/p>\n<\/td>\n

            		\n

            V+<\/span><\/p>\n<\/td>\n

            		\n

            V+<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n c\u1ea5p ngu\u1ed3n \u0111\u1ea7u v\u00e0o t\u1eeb 5 \u0111\u1ebfn 24V<\/span><\/td>\n<\/tr>\n
            \n

            VDD<\/span><\/p>\n<\/td>\n

            		\n

            VDD<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n c\u1ea5p ngu\u1ed3n 5V<\/span><\/td>\n<\/tr>\n
            \n

            ON5<\/span><\/p>\n<\/td>\n

            		\n

            ON1<\/span><\/p>\n<\/td>\n

            		L\u1ec7nh m\u1edf ngu\u1ed3n v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            \n

            BST5<\/span><\/p>\n<\/td>\n

            		\n

            BST1<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n b\u00f9 \u0111i\u1ec7n \u00e1p v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            \n

            DH5<\/span><\/p>\n<\/td>\n

            		\n

            DH1<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n dao \u0111\u1ed9ng ra m\u1ee9c cao v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            \n

            LX5<\/span><\/p>\n<\/td>\n

            		\n

            LX1<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n n\u1ed1i v\u1edbi \u0111i\u1ec3m gi\u1eefa hai Mosfet v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            \n

            DL5<\/span><\/p>\n<\/td>\n

            		\n

            DL1<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n dao \u0111\u1ed9ng ra m\u1ee9c th\u1ea5p v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            \n

            FB5<\/span><\/p>\n<\/td>\n

            		\n

            FB1<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n h\u1ed3i ti\u1ebfp \u0111\u1ec3 \u1ed5n \u0111\u1ecbnh \u00e1p ra v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            \n

            CSH5<\/span><\/p>\n<\/td>\n

            		\n

            CS1<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n c\u1ea3m bi\u1ebfn d\u00f2ng v\u1ebf 1<\/span><\/td>\n<\/tr>\n
            \n

            CSL5<\/span><\/p>\n<\/td>\n<\/tr>\n

            \n

            ON3<\/span><\/p>\n<\/td>\n

            		\n

            ON2<\/span><\/p>\n<\/td>\n

            		L\u1ec7nh m\u1edf ngu\u1ed3n v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            \n

            BST3<\/span><\/p>\n<\/td>\n

            		\n

            BST2<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n b\u00f9 \u0111i\u1ec7n \u00e1p v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            \n

            DH3<\/span><\/p>\n<\/td>\n

            		\n

            DH2<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n dao \u0111\u1ed9ng ra m\u1ee9c cao v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            \n

            LX3<\/span><\/p>\n<\/td>\n

            		\n

            LX2<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n n\u1ed1i v\u1edbi \u0111i\u1ec3m gi\u1eefa hai Mosfet v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            \n

            DL3<\/span><\/p>\n<\/td>\n

            		\n

            DL2<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n dao \u0111\u1ed9ng ra m\u1ee9c th\u1ea5p v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            \n

            FB3<\/span><\/p>\n<\/td>\n

            		\n

            FB2<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n h\u1ed3i ti\u1ebfp \u0111\u1ec3 \u1ed5n \u0111\u1ecbnh \u00e1p ra v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            \n

            CSH3<\/span><\/p>\n<\/td>\n

            		\n

            CS2<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n c\u1ea3m bi\u1ebfn d\u00f2ng v\u1ebf 2<\/span><\/td>\n<\/tr>\n
            \n

            CSL3<\/span><\/p>\n<\/td>\n<\/tr>\n

            \n

            P.GOOD<\/span><\/p>\n<\/td>\n

            		\n

            P.GOOD<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n b\u00e1o ngu\u1ed3n t\u1ed1t<\/span><\/td>\n<\/tr>\n
            \n

            REF<\/span><\/p>\n<\/td>\n

            		\n

            REF<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n ra \u0111i\u1ec7n \u00e1p chu\u1ea9n<\/span><\/td>\n<\/tr>\n
            \n

            Ch\u00e2n kh\u00e1c nhau<\/span><\/p>\n<\/td>\n

            		\n

            VL (LDO, VREG)<\/span><\/p>\n<\/td>\n

            		\n

            kh\u00f4ng c\u00f3<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n All_Always_on ra \u0111i\u1ec7n \u00e1p 5V<\/span><\/td>\n<\/tr>\n
            \n

            SHDN<\/span><\/p>\n<\/td>\n

            		\n

            kh\u00f4ng c\u00f3<\/span><\/p>\n<\/td>\n

            		Ch\u00e2n Shutdown – ch\u00e2n b\u1ea3o v\u1ec7<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

            4 – Ph\u01b0\u01a1ng ph\u00e1p ki\u1ec3m tra ngu\u1ed3n th\u1ee9 c\u1ea5p b\u1eb1ng ngu\u1ed3n \u0111a n\u0103ng<\/strong><\/span><\/h2>\n

            a – Tr\u01b0\u1eddng h\u1ee3p sau \u0111\u00e2y cho th\u1ea5y m\u00e1y c\u00f3 ngu\u1ed3n c\u1ea5p tr\u01b0\u1edbc nh\u01b0ng kh\u00f4ng c\u00f3 ngu\u1ed3n th\u1ee9 c\u1ea5p, khi \u0111\u00f3 m\u00e1y \u0103n d\u00f2ng kho\u1ea3ng 0,03A nh\u01b0ng khi b\u1ea5m c\u00f4ng t\u1eafc m\u1edf ngu\u1ed3n, d\u00f2ng ti\u00eau th\u1ee5 c\u1ee7a m\u00e1y kh\u00f4ng t\u0103ng.<\/span><\/p>\n

            \"Tr\u01b0\u1eddng
            <\/span> Tr\u01b0\u1eddng h\u1ee3p a<\/span><\/figcaption><\/figure>\n

            b – Tr\u01b0\u1eddng h\u1ee3p sau \u0111\u00e2y khi ta b\u1ea5m c\u00f4ng t\u1eafc, d\u00f2ng ti\u00eau th\u1ee5 c\u1ee7a m\u00e1y t\u0103ng l\u00ean nh\u01b0ng ch\u1ec9 t\u0103ng \u0111\u1ebfn kho\u1ea3ng 0,3A th\u00ec d\u1eebng l\u1ea1i, \u0111i\u1ec1u n\u00e0y ngh\u0129a l\u00e0 m\u00e1y \u0111\u00e3 xu\u1ea5t hi\u1ec7n c\u00e1c \u0111i\u1ec7n \u00e1p th\u1ee9 c\u1ea5p nh\u01b0ng CPU v\u1eabn ch\u01b0a ho\u1ea1t \u0111\u1ed9ng.<\/span><\/p>\n<\/div>\n

            \"Tr\u01b0\u1eddng
            <\/span> Tr\u01b0\u1eddng h\u1ee3p b<\/span><\/figcaption><\/figure>\n","protected":false},"excerpt":{"rendered":"

            Ngu\u1ed3n th\u1ee9 c\u1ea5p l\u00e0 ngu\u1ed3n \u0111i\u1ec7n xu\u1ea5t hi\u1ec7n sau khi ta b\u1ea5m c\u00f4ng t\u1eafc m\u1edf ngu\u1ed3n. Ngu\u1ed3n th\u1ee9 c\u1ea5p bao g\u1ed3m to\u00e0n b\u1ed9 c\u00e1c \u0111i\u1ec7n \u00e1p cung c\u1ea5p cho c\u00e1c b\u1ed9 ph\u1eadn c\u1ee7a m\u00e1y \u0111\u1ec3 chu\u1ea9n b\u1ecb \u0111\u01b0a m\u00e1y v\u00e0o ch\u1ebf \u0111\u1ed9 ho\u1ea1t \u0111\u1ed9ng.<\/p>\n","protected":false},"author":95,"featured_media":12111,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[96,94],"tags":[687],"_links":{"self":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts\/1524"}],"collection":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/users\/95"}],"replies":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1524"}],"version-history":[{"count":0,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/posts\/1524\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=\/wp\/v2\/media\/12111"}],"wp:attachment":[{"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1524"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1524"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hocvienit.vn\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1524"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}