{"id":11762,"date":"2020-02-08T02:11:06","date_gmt":"2020-02-08T02:11:06","guid":{"rendered":"https:\/\/hocvienit.vn\/?p=11762"},"modified":"2024-07-03T15:06:01","modified_gmt":"2024-07-03T08:06:01","slug":"so-sanh-ddr3-va-ddr4-nen-chon-loai-ram-nao","status":"publish","type":"post","link":"https:\/\/hocvienit.vn\/?p=11762","title":{"rendered":"So s\u00e1nh DDR3 v\u00e0 DDR4 – N\u00ean ch\u1ecdn lo\u1ea1i RAM n\u00e0o?"},"content":{"rendered":"

B\u1ea1n mu\u1ed1n n\u00e2ng c\u1ea5p RAM m\u00e1y t\u00ednh? B\u1ea1n kh\u00f4ng bi\u1ebft n\u00ean l\u1ef1a ch\u1ecdn lo\u1ea1i RAM m\u00e1y t\u00ednh n\u00e0o l\u00e0 ph\u00f9 h\u1ee3p nh\u1ea5t v\u1edbi m\u00ecnh? B\u1ea1n \u0111ang ph\u00e2n v\u00e2n gi\u1eefa DDR3 v\u00e0 DDR4? B\u00e0i vi\u1ebft d\u01b0\u1edbi \u0111\u00e2y s\u1ebd c\u00f3 c\u00e2u tr\u1ea3 l\u1eddi cho t\u1ea5t c\u1ea3 c\u00e1c v\u1ea5n \u0111\u1ec1 tr\u00ean.<\/span><\/p>\n

\"So
So s\u00e1nh DDR3 v\u00e0 DDR4 – N\u00ean ch\u1ecdn lo\u1ea1i RAM n\u00e0o?<\/figcaption><\/figure>\n

Gi\u1edbi thi\u1ec7u v\u1ec1 DDR3 v\u00e0 DDR4<\/strong><\/h2>\n

RAM<\/span><\/a> l\u00e0 vi\u1ebft t\u1eaft c\u1ee7a c\u1ee5m t\u1eeb Ti\u1ebfng Anh: \u201cRandom Access Memory\u201d. N\u00f3 l\u00e0 m\u1ed9t lo\u1ea1i b\u1ed9 nh\u1edb c\u00f3 kh\u1ea3 bi\u1ebfn truy xu\u1ea5t \u0111\u1ecdc-ghi ng\u1eabu nhi\u00ean \u0111\u1ebfn b\u1ea5t k\u1ef3 v\u1ecb tr\u00ed n\u00e0o trong b\u1ed9 nh\u1edb d\u1ef1a theo \u0111\u1ecba ch\u1ec9 \u00f4 nh\u1edb. Nh\u01b0ng nh\u1eefng th\u00f4ng tin \u0111\u01b0\u1ee3c l\u01b0u tr\u00ean RAM ch\u1ec9 l\u00e0 t\u1ea1m th\u1eddi cho n\u00ean ch\u00fang s\u1ebd m\u1ea5t \u0111i khi m\u1ea5t ngu\u1ed3n \u0111i\u1ec7n cung c\u1ea5p.<\/span><\/p>\n

Hi\u1ec7n nay c\u00f3 r\u1ea5t nhi\u1ec1u <\/span>c\u00f4ng ngh\u1ec7 RAM<\/span><\/a> nh\u01b0: Dram, Sram, SDram\u2026 Trong \u0111\u00f3, c\u00f3 hai th\u1ebf h\u1ec7 \u0111ang nh\u1eadn \u0111\u01b0\u1ee3c nhi\u1ec1u s\u1ef1 quan t\u00e2m nh\u1ea5t t\u1eeb ph\u00eda ng\u01b0\u1eddi d\u00f9ng \u0111\u00f3 l\u00e0 DDR3 v\u00e0 DDR4.<\/span><\/p>\n

 <\/p>\n

DDR3<\/span><\/h3>\n

DDR3 \u0111\u01b0\u1ee3c ra \u0111\u1eddi v\u00e0o n\u0103m 2007. \u0110\u00e2y l\u00e0 phi\u00ean b\u1ea3n n\u00e2ng c\u1ea5p t\u1eeb DDR2. Trong \u0111\u00f3, DDR3 \u0111\u01b0\u1ee3c gia t\u0103ng t\u1ed1c \u0111\u1ed9 truy\u1ec1n t\u1ea3i l\u00ean t\u1edbi 800-2133 MHz v\u00e0 s\u1eed d\u1ee5ng m\u1ee9c \u0111i\u1ec7n \u00e1p l\u00e0 1.5V. Th\u1ebf h\u1ec7 n\u00e0y \u0111\u01b0\u1ee3c trang b\u1ecb m\u1ee9c dung l\u01b0\u1ee3ng t\u1ed1i \u0111a l\u00e0 8GB m\u1ed7i m\u00f4-\u0111un v\u1edbi t\u1ed1c \u0111\u1ed9 th\u1ea5p nh\u1ea5t l\u00e0 800 tri\u1ec7u MT\/s. \u0110\u1ed9 tr\u1ec5 c\u1ee7a DDR3 l\u00e0 12,5ms.<\/span><\/p>\n

\"DDR3\"
DDR3<\/figcaption><\/figure>\n

DDR4<\/span><\/h3>\n

DDR3 \u0111\u01b0\u1ee3c ra \u0111\u1eddi v\u00e0o n\u0103m 2014. \u0110\u00e2y l\u00e0 phi\u00ean b\u1ea3n n\u00e2ng c\u1ea5p t\u1eeb DDR3. Trong \u0111\u00f3, DDR4 \u0111\u01b0\u1ee3c gia t\u0103ng t\u1ed1c \u0111\u1ed9 truy\u1ec1n t\u1ea3i l\u00ean t\u1edbi 2133-4266 MHz v\u00e0 ch\u1ec9 s\u1eed d\u1ee5ng m\u1ee9c \u0111i\u1ec7n \u00e1p l\u00e0 1.2V. Th\u1ebf h\u1ec7 n\u00e0y \u0111\u01b0\u1ee3c trang b\u1ecb m\u1ee9c dung l\u01b0\u1ee3ng t\u1ed1i \u0111a r\u1ea5t l\u1edbn, ch\u1ea1m ng\u01b0\u1ee1ng 16GB m\u1ed7i m\u00f4-\u0111un v\u1edbi t\u1ed1c \u0111\u1ed9 th\u1ea5p nh\u1ea5t \u0111\u00e3 l\u00e0 1600 tri\u1ec7u MT\/s. \u0110\u1ed9 tr\u1ec5 c\u1ee7a DDR3 l\u00e0 12,75ms. \u0110\u1eb7c bi\u1ec7t, RAM DDR4 c\u0169ng c\u00f3 gi\u00e1 \u0111\u1eaft h\u01a1n DDR3.<\/span><\/p>\n

\"DDR4\"
DDR4<\/figcaption><\/figure>\n

So s\u00e1nh DDR3 v\u00e0 DDR4<\/strong><\/h2>\n

T\u1eeb c\u00e1c th\u00f4ng s\u1ed1 tr\u00ean c\u1ee7a DDR3 v\u00e0 DDR4 ta c\u00f3 th\u1ec3 r\u00fat ra k\u1ebft lu\u1eadn sau:<\/span><\/p>\n